IDT7M1001 查看數據表（PDF） - Integrated Device Technology

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IDT7M1001

128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

Integrated Device Technology 

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY(1)

t WC

ADDR R

MATCH

R/W R

t WP

DATA IN R

t DH

t DW

VALID

ADDR L

MATCH

DATA OUT L

NOTE:

1. L_CS = R_CS = LOW.

t WDD

t DDD

WRITE CYCLE LEFT PORT

TRUTH TABLES

TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)

Inputs(1)

CS R/W

OE

H

X

X

L

L

X

L

H

L

X

X

H

NOTE:

1. AOL — A12 ≠ A0R — A12R

SEM

H

H

H

X

Outputs

I/O0 - I/O7

High-Z

DATAIN

DATAOUT

High-Z

Mode

Deselected: Power Down

Write to Both Bytes

Read Both Bytes

Outputs Disabled

TABLE II: SEMAPHORE READ/WRITE CONTROL(1)

Inputs

CS R/W

OE

H

H

L

X

X

L

X

X

NOTE:

1. AOL — A12 ≠ A0R — A12R

SEM

L

L

L

Outputs

I/O0 - I/O7

DATAOUT

DATAIN

—

Mode

Read Data in Semaphore Flag

Write DIN0 into Semaphore Flag

Not Allowed

VALID

READ CYCLE

RIGHT PORT

2804 drw 12

2804 tbl 10

2804 tbl 11

SEMAPHORE OPERATION

For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.

7.5

9

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