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IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2052E

DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT

LOS/AIS

LOS

Detector

RTIP

RRING

Receive

Internal

termination

Monitor Gain/

Adaptive Equalizer

Data Slicer

Clock

and Data

Recovery

Jitter

Attenuator

Decoder

RCLK

RDP

RDN

Figure-5 Receive Path Function Block Diagram

Table-5 Impedance Matching for Receiver

Cable Configuration

Internal Termination

R_TERM[2:0]

E1 / 75 Ω

000

E1 / 120 Ω

001

RR

120 Ω

External Termination

R_TERM[2:0]

1XX

RR

75 Ω

120 Ω

A

RX Line

B

TX Line

• 1:1•

•2:1•

VDDRn

D8

One of the Two Identical Channels

•

•· RTIPn

D7

VDDRn

RR4 VDDRn

D6

• D5 •· VDDTn

RT4

D4

•·

D3

Cp2

VDDTn

D2

RT4

3 •·

D1

RRINGn

TTIPn

TRINGn

0.1µF

GNDRn

•

VDDTn

0.1µF

GNDTn

•

3.3 V

68µF1

3.3 V

68µF1

Note:

1. Common decoupling capacitor. One per chip

2. Cp 0-560 (pF)

3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060

4. RT/ RR: refer to Table-4 and Table-5 respecivley for RT and RR values

Figure-6 Transmit/Receive Line Circuit

In hardware control mode, TERMn, PULSn pins can be used to select

impedance matching for both receiver and transmitter on a per channel

basis. If TERMn pin is low, internal impedance network will be used. If

TERMn pin is high, external impedance network will be used. When internal

impedance network is used, PULSn pins should be set to select specific

internal impedance for the corresponding channel. Refer to 5 HARDWARE

CONTROL PIN SUMMARY for details.

3.3.2 LINE MONITOR

The non-intrusive monitoring on channels located in other chips can be

performed by tapping the monitored channel through a high impedance

bridging circuit. Refer to Figure-7 and Figure-8.

After a high resistance bridging circuit, the signal arriving at the RTIPn/

RRINGn is dramatically attenuated. To compensate this attenuation, the

Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,

selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor

Gain should be set to 0 dB.

In hardware control mode, MONTn pin can be used to set the Monitor

Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for

the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for

the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUM-

MARY for details.

FUNCTIONAL DESCRIPTION

21

December 12, 2005

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