IDT82V2058(2004) 查看數據表（PDF） - Integrated Device Technology

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IDT82V2058
(Rev.:2004)

OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

OVERVIEW

The IDT82V2058 is a fully integrated octal short-haul line interface

unit, which contains eight transmit and receive channels for use in E1

applications. The receiver performs clock and data recovery. As an

option, the raw sliced data (no retiming) can be output to the system.

Transmit equalization is implemented with low-impedance output driv-

ers that provide shaped waveforms to the transformer, guaranteeing

template conformance. A selectable jitter attenuation may be placed in

the receive path or the transmit path. Moreover, multiple testing func-

tions, such as error detection, loopback and JTAG boundary scan are

also provided. The device is optimized for flexible software control

through a serial or parallel host mode interface. Hardware control is

also available. Figure-1 shows One of the Eight Identical Channels

operation.

SYSTEM INTERFACE

The system interface of each channel can be configured to

operate in different modes:

1. Single Rail interface with clock recovery.

2. Dual Rail interface with clock recovery.

3. Dual Rail interface with data recovery (that is, with raw data slic-

ing only and without clock recovery).

Therefore, each signal pin on system side has multiple functions

depending on which operation mode the device is in.

Dual Rail interface consists of TDPn1, TDNn, TCLKn, RDPn, RDNn

and RCLKn. Data transmitted from TDPn and TDNn appears on

TTIPn and TRINGn at the line interface; data received from the RTIPn

and RRINGn at the line interface are transferred to RDPn and RDNn

while the recovered clock extracting from the received data stream

outputs on RCLKn. In Dual Rail operation, the clock/data recovery

mode is selectable. Dual Rail interface with clock recovery shown in

Figure-3 is a default configuration mode. Dual Rail interface with data

recovery is shown in Figure-4. Pin RDPn and RDNn, in this condition,

are raw RZ slice output and internally connected to an EXOR which is

fed to the RCLKn output for external clock recovery applications.

In Single Rail mode, data transmitted from TDn appears on TTIPn

and TRINGn at the line interface. Data received from the RTIPn and

RRINGn at the line interface appears on RDn while the recovered

clock extracting from the received data stream outputs on RCLKn.

When the device is in Single Rail interface, the selectable AMI or

HDB3 line encoder/decoder is available and any code violation in the

received data will be indicated at the CVn pin. The Single Rail mode

can be divided into 2 sub-modes. Single Rail mode1, whose interface

is composed of TDn, TCLKn, RDn, CVn and RCLKn, is realized by

pulling pin TDNn to high for more than 16 consecutive TCLK cycles.

Single Rail mode 2, whose interface is composed of TDn, TCLKn,

RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in e-

CRS2 and bit SING in e-SING. The difference between them is that, in

the latter mode bipolar violation can be inserted via pin BPVIn if AMI

line code is selected.

The configuration of different system interface is summarized in

Table-1.

CLOCK EDGES

The active edge of RCLK and SCLK(serial interface clock) are also

selectable. If pin CLKE is Low, the active edge of RCLK is the rising

edge, as for SCLK, that is falling edge. On the contrary, if CLKE is

High, the active edge of RCLK is the falling edge and that of SCLK is

rising edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active

high, and those output signals are valid on the active edge of RCLK

and SCLK respectively. See Table-2 for details. However, in dual rail

mode without clock recovery, pin CLKE is used to set the active level

for RDPn/RDNn raw slicing output: High for active high polarity and

Low for active low. It should be noted that data on pin SDI are always

active high and is sampled on the rising edge of SCLK. The data on

pin TD/TDP or BPVI/TDN are also always active high but is sampled

on the falling edge of TCLK, despite the level on CLKE.

RTIPn

RRINGn

Slicer

LOS

Detector

CLK&Data

Recovery

(DPLL)

One of Eight Identical Channels

Jitter

Attenuator

HDB3/

AMI

Decoder

TTIPn

TRINGn

Peak

Detector

Line

Driver

Waveform

Shaper

Jitter

Attenuator

HDB3/

AMI

Encoder

Transmit

All Ones

Figure - 3. Dual Rail Interface with Clock Recovery 3

NOTE:

1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels

2. The first letter “e-”indicates expanded register.

3. The grey blocks are bypassed and the dotted blocks are selectable

11

LOSn

RCLKn

RDPn

RDNn

TCLKn

TDPn

TDNn

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