IDT82V2058-10 查看數據表（PDF） - Integrated Device Technology
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IDT82V2058-10 Datasheet PDF : 53 Pages
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IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
CLKE
TRST
TMS
TCK
TDO
TDI
VDDIO
GNDIO
VDDT0
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
GNDT0
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
VDDD
VDDA
Type
I
I
Pull-up
I
Pull-up
I
O
High-Z
I
Pull-up
-
-
-
-
-
Pin No.
TQFP144 PBGA160
Description
CLKE: Clock Edge Select
115
E13
The signal on this pin determines the active edge of RCLKn and SCLK in clock recovery mode, or deter-
mines the active level of RDPn and RDNn in the data recovery mode. See 2.2 Clock Edges on page 14 for
details.
JTAG Signals
TRST: JTAG Test Port Reset (Active Low)
95
G12 This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor
and it can be left open.
TMS: JTAG Test Mode Select
96
F11 The signal on this pin controls the JTAG test performance and is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and it can be left open.
TCK: JTAG Test Clock
97
F14
This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on the ris-
ing edges of TCK, while the data on TDO is clocked out of the device on the falling edges of TCK. This pin
should be connected to GNDIO or VDDIO pin when unused.
TDO: JTAG Test Data Output
98
F13
This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on the fall-
ing edges of TCK. TDO is a high-Z output signal. It is active only when scanning of data is out. This pin
should be left float when unused.
TDI: JTAG Test Data Input
99
F12 This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and it can be left open.
Power Supplies and Grounds
17
92
G1
G14
3.3 V I/O Power Supply
18
91
G4
G11
I/O GND
44
N4, P4
53
L4, M4
56
65
116
125
L11, M11
N11, P11
A11, B11
C11, D11
3.3 V/5 V Power Supply for Transmitter Driver
All VDDT pins must be connected to 3.3 V or all VDDT must be connected to 5 V. It is not allowed to leave
any of the VDDT pins open (not-connected) even if the channel is not used.
128
C4, D4
137
A4, B4
47
N6, P6
50
L6, M6
59
L9, M9
62
119
N9, P9
A9, B9
Analog GND for Transmitter Driver
122
C9, D9
131
C6, D6
134
A6, B6
19
90
H1
H14
3.3 V Digital/Analog Core Power Supply
10
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