IN74ACT373N 查看數據表（PDF） - IK Semicon Co., Ltd

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IN74ACT373N

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

IK Semicon Co., Ltd 

IN74ACT373

AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Symbol

Parameter

tPLH Propagation Delay, Input D to Q (Figure 1)

tPHL Propagation Delay, Input D to Q (Figure 1)

tPLH Propagation Delay, Latch Enable to Q (Figure 2)

tPHL Propagation Delay, Latch Enable to Q (Figure 2)

tPZH Propagation Delay, Output Enable to Q

(Figure 3)

tPZL Propagation Delay, Output Enable to Q

(Figure 3)

tPHZ Propagation Delay, Output Enable to Q

(Figure 3)

tPLZ Propagation Delay, Output Enable to Q

(Figure 3)

CIN Maximum Input Capacitance

Guaranteed Limits

25 °C

-40°C to 85°C Unit

Min Max Min Max

2.5 10 1.5 11.5 ns

2.0 10 1.5 11.5 ns

2.5 11 2.0 11.5 ns

2.0 10 1.5 11.5 ns

2.0 9.5 1.5 10.5 ns

2.0 9.0 1.5 10.5 ns

2.5 11 2.5 12.5 ns

1.5 8.5 1.0 10 ns

4.5

4.5

pF

CPD Power Dissipation Capacitance

Typical @25°C,VCC=5.0 V

40

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Symbol

tsu

th

tw

Parameter

Minimum Setup Time, Input D to Latch Enable

(Figure 4)

Minimum Hold Time, Latch Enable to

Input D (Figure 4)

Minimum Pulse Width, Latch Enable

(Figure 2)

Guaranteed Limits

25 °C

-40°C to 85°C Unit

7.0

8.0

ns

0

1.0

ns

2.0

8.0

ns

Rev. 00

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