INT5130CS 查看數據表（PDF） - Unspecified

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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

arbitrary amount of time, while the INT5130 is gaining access to the channel and transmitting the

packet.

MII_CRS does not affect the receive side of the channel. Once packets start arriving from the

powerline medium and begin transmission to the external host controller over the MII interface, the

external host MUST be ready to receive or the packet can be lost. Note that external MACs

programmed to run in 100 Mbps mode do not use a jabber timeout, so there is no timing restriction

on how long MII_CRS can be asserted.

MII_CRS

MII_TXEN

MII_TX[3:1], MII_TX0

Internal TX buffer available pulse

MII_RX[3:0]

MII_RXDV

Internal RX buffer available pulse

MII_COL

320 ns

(32 Bit times)

320 ns

(32 Bit times)

320 ns

(32 Bit times)

320 ns

(32 Bit times)

P

P

P

P

P

Case 1

TX only

Case 2

RX Only

Case 3

RX while TX, delayed TX buffer avail

Case 4

RX while no TX buf avail

Figure 8: MII Flow Control Overview Part 1

Case 5

TX Buf avail

INTELLON CONFIDENTIAL

15

Rev 8.1

ADVANCE INFORMATION

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