NM24C04U 查看數據表（PDF） - Fairchild Semiconductor

零件编号

产品描述 (功能)

比赛名单

NM24C04U

4K-Bit Serial EEPROM 2-Wire Bus Interface

Fairchild Semiconductor 

Write Operations

BYTE WRITE

For a write operation a second address field is required which is

a word address that is comprised of eight bits and provides access

to any one of the 256 bytes in the selected page of memory. Upon

receipt of the byte address the NM24C04U/05U responds with an

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the

NM24C04U/05U begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress the

NM24C04U/05U inputs are disabled, and the device will not

respond to any requests from the master. Refer to Figure 6 for the

address, acknowledge and data transfer sequence.

PAGE WRITE

The NM24C04U/05U is capable of a sixteen byte page write

operation. It is initiated in the same manner as the byte write

operation; but instead of terminating the write cycle after the first

data byte is transferred, the master can transmit up to fifteen more

bytes. After the receipt of each byte, the NM24C04U/05U will

respond with an acknowledge.

After the receipt of each byte, the internal address counter

increments to the next address and the next SDA data is accepted.

If the master should transmit more than sixteen bytes prior to

generating the stop condition, the address counter will "roll over"

and the previously written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 7 for the address, acknowl-

edge, and data transfer sequence.

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s

write operation the NM24C04U/05U initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuing the start condition followed by the slave address for a write

operation. If the NM24C04U/05U is still busy with the write

operation no ACK will be returned. If the NM24C04U/05U has

completed the write operation an ACK will be returned and the

host can then proceed with the next read or write operation.

Write Protection (NM24C05U Only)

Programming of the upper half of the memory will not take place

if the WP pin of the NM24C05U is connected to VCC. The

NM24C05U will accept slave and byte addresses; but if the

memory accessed is write protected by the WP pin, the NM24C05U

will not generate an acknowledge after the first byte of data has

been received, and thus the program cycle will not be started when

the stop condition is asserted.

Byte Write (Figure 6)

Bus Activity:

Master

S

T

A

SLAVE

R ADDRESS

T

SDA Line

A

Bus Activity:

C

NM24C04U/05U

K

WORD

ADDRESS

A

C

K

S

T

DATA

O

P

A

C

K

DS800008-15

Page Write (Figure 7)

Bus Activity:

Master

SDA Line

S

T

A

SLAVE

R ADDRESS

T

Bus Activity:

NM24C04U/05U

WORD ADDRESS (n)

A

A

C

C

K

K

DATA n

DATA n + 1

S

T

DATA n + 15

O

P

A

A

A

C

C

C

K

K

K

DS800008-16

10

NM24C04U/NM24C05U Rev. C.1

www.fairchildsemi.com

Share Link: