FP4368PBF 查看數據表（PDF） - International Rectifier
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FP4368PBF Datasheet PDF : 8 Pages
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IRFP4368PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
75 ––– ––– V VGS = 0V, ID = 250µA
––– 0.077 ––– V/°C Reference to 25°C, ID = 5mAd
––– 1.46 1.85 mΩ VGS = 10V, ID = 195A g
2.0 ––– 4.0 V VDS = VGS, ID = 250µA
––– ––– 20 µA VDS = 75V, VGS = 0V
IGSS
Gate-to-Source Forward Leakage
––– ––– 250
––– ––– 100
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
Gate-to-Source Reverse Leakage
––– ––– -100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Qg
Qgs
Qgd
Qsync
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
650 ––– ––– S VDS = 50V, ID = 195A
––– 380 570 nC ID = 195A
––– 79 –––
VDS = 38V
––– 105 –––
VGS = 10V g
––– 275 –––
ID = 195A, VDS =0V, VGS = 10V
RG(int)
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Internal Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 0.80 –––
––– 43 –––
––– 220 –––
––– 170 –––
––– 260 –––
––– 19230 –––
––– 1670 –––
––– 770 –––
Ω
ns VDD = 49V
ID = 195A
RG = 2.7Ω
VGS = 10V g
pF VGS = 0V
VDS = 50V
ƒ = 100kHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)i ––– 1700 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)h ––– 1410 –––
VGS = 0V, VDS = 0V to 60V i
VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
(Body Diode) di
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
––– ––– 350c A MOSFET symbol
D
showing the
––– ––– 1280
integral reverse
G
p-n junction diode.
S
––– ––– 1.3 V TJ = 25°C, IS = 195A, VGS = 0V g
––– 130 200 ns TJ = 25°C
VR = 64V,
––– 140 210
TJ = 125°C
––– 450 680 nC TJ = 25°C
IF = 195A
di/dt = 100A/µs g
––– 530 800
TJ = 125°C
––– 9.1 ––– A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction ISD ≤ 195A, di/dt ≤ 1740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
temperature. Bond wire current limit is 195A. Note that current
Pulse width ≤ 400µs; duty cycle ≤ 2%.
limitations arising from heating of the device leads may occur with Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. Refer to App Notes (AN-1140).
as Coss while VDS is rising from 0 to 80% VDSS.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
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