CA5160 查看數據表（PDF） - Intersil
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CA5160 Datasheet PDF : 18 Pages
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CA5160
4000
1000
VS = ±7.5V
100
10
1
-80 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (oC)
FIGURE 2. INPUT CURRENT vs TEMPERATURE
Input Offset Voltage (VIO) Variation with DC Bias vs
Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magni-
tude of the change is increased at high temperatures. Users
of the CA5160 should be alert to the possible impacts of this
effect if the application of the device involves extended opera-
tion at high temperatures with a significant differential DC bias
voltage applied across Terminals 2 and 3. Figure 3 shows typ-
ical data pertinent to shifts in offset voltage encountered with
CA5160 devices in metal can packages during life testing. At
lower temperatures (metal can and plastic) for example at
85oC, this change in voltage is considerably less. In typical lin-
ear applications where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage. The 2VDC
differential voltage example represents conditions when the
amplifier output state is “toggled”, e.g., as in comparator appli-
cations.
7
TA = 125oC FOR METAL CAN PACKAGES
6
DIFFERENTIAL DC VOLTAGE
5 (ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
4
3
2
DIFFERENTIAL DC VOLTAGE
1
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+/2
0
0 500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)
FIGURE 3. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
Power Supply Considerations
Because the CA5160 is very useful in single-supply applica-
tions, it is pertinent to review some considerations relating to
power-supply current consumption under both single-and
dual-supply service. Figures 4A and 4B show the CA5160
connected for both dual and single-supply operation.
Dual-supply Operation: When the output voltage at Termi-
nal 6 is 0V, the currents supplied by the two power supplies
are equal. When the gate terminals of Q8 and Q12 are
driven increasingly positive with respect to ground, current
flow through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single Supply Operation: Initially, let it be assumed that the
value of RL is very high (or disconnected), and that the input-
terminal bias (Terminals 2 and 3) is such that the output termi-
nal (Number 6) voltage is at V+/2, i.e., the voltage-drops
across Q8 and Q12 are of equal magnitude. Figure 21 shows
typical quiescent supply-current vs supply-voltage for the
CA5160 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage transfer characteristics (see Figure 20). If either
Q8 or Q12 are swung out of their linear regions toward cutoff
(a nonlinear region), there will be a corresponding reduction in
supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q12 is completely cut off and the supply-current to
series-connected transistors Q8, Q12 goes essentially to zero.
The two preceding stages in the CA5160, however, continue
to draw modest supply-current (see the lower curve in Figure
21) even through the output stage is strobed off. Figure 4A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming RL = ∞, by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 4B. Let it further be assumed
again that the input terminal bias (Terminals 2 and 3) is such
that the output terminal (Number 6) voltage is V+/2. Since
PMOS transistor Q8 must now supply quiescent current to
both RL and transistor Q12, it should be apparent that under
these conditions the supply current must increase as an
inverse function of the RL magnitude. Figure 27 shows the
voltage drop across PMOS transistor Q8 as a function of
load current at several supply voltages. Figure 20 shows the
voltage transfer characteristics of the output stage for sev-
eral values of load resistance.
3-7
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