IS61WV12816DALL(2008) 查看數據表（PDF） - Integrated Silicon Solution

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IS61WV12816DALL
(Rev.:2008)

128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

Integrated Silicon Solution 

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,

IS64WV12816DBLL/DBLS

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)

ADDRESS

DOUT

t RC

PREVIOUS DATA VALID

t OHA

t AA

t OHA

DATA VALID

READ1.eps

READ CYCLE NO. 2(1,3)

ADDRESS

OE

CE

LB, UB

tLZCE

DOUT

tLZB

HIGH-Z

tRC

tAA

tOHA

tDOE

tLZOE

tACE

tHZOE

tHZCE

tBA

tRC

tHZB

DATA VALID

VDD

Supply

Current

tPU

50%

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = VIL.

3. Address is valid prior to or coincident with CE LOW transition.

tPD

ICC

50%

ISB

UB_CEDR2.eps

1

2

3

4

5

6

7

8

9

10

11

12

Integrated Silicon Solution, Inc. — www.issi.com

11

Rev. C

05/01/08

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