ISL8013 查看數據表（PDF） - Intersil

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ISL8013

3A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator

Intersil 

ISL8013

Pin Descriptions

VIN

Input supply voltage. Connect a 10µF ceramic capacitor to

power ground.

VDD

Input supply voltage for the analog circuitry. Connect to VIN

pin.

EN

Regulator enable pin. Enable the output when driven to high.

Shut down the chip and discharge output capacitor when

driven to low. Do not leave this pin floating.

PG

1ms timer output. At power-up or EN HI, this output is a 1ms

delayed Power-Good signal for the output voltage.

SYNCH

Mode Selection pin. Connect to logic high or input voltage

VDD for PWM mode. Connect to logic low or ground for PFM

mode. Connect to an external function generator for

synchronization with the negative edge trigger. Do not leave

this pin floating.

LX

Switching node connection. Connect to one terminal of the

inductor.

PGND

Power ground.

SGND

Signal ground.

VFB

Buck regulator output feedback. Connect to the output

through a resistor divider for adjustable output voltage. For

0.8V output voltage, connect this pin to the output.

NC

No connect.

Exposed Pad

The exposed pad must be connected to the SGND pin for

proper electrical performance. Place as much vias as

possible under the pad connecting to SGND plane for

optimal thermal performance.

6

FN6309.1

December 27, 2007

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