K4S560832B 查看數據表（PDF） - Samsung

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K4S560832B

256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

Samsung 

K4S560832B

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter

Operating current

(One bank active)

Symbol

Test Condition

Burst length = 1

ICC1 tRC ≥ tRC(min)

IO = 0 mA

Version

Unit Note

-75 -1H -1L

120 110 110 mA 1

Precharge standby current in

power-down mode

ICC2P CKE ≤ VIL(max), tCC = 10ns

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞

2

mA

2

Precharge standby current in

ICC2N

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

16

non power-down mode

ICC2NS

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

14

mA

Active Standby current

in power-down mode

ICC3P CKE ≤ VIL(max), tCC = 10ns

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞

6

mA

6

Active standby current in

ICC3N

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

30

mA

non power-down mode

(One bank active)

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable

25

mA

Operating current

(Burst mode)

Refresh current

Self refresh current

IO = 0 mA

ICC4 Page burst

4banks activated.

tCCD = 2CLKs

ICC5 tRC ≥ tRC(min)

ICC6 CKE ≤ 0.2V

140 115 115 mA 1

220 210 210 mA 2

C

3

mA 3

L

2

mA 4

Notes : 1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S560832B-TC**

4. K4S560832B-TL**

5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

Rev. 0.2 May.2000

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