KS0108B 查看數據表（PDF） - Samsung
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KS0108B Datasheet PDF : 17 Pages
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KS0108B
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCIPTION
PIN (NO)
3
78
73, 8
SYMBOL
VDD
VSS
VEE1.2
74, 7
76, 5
77, 4
75, 6
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
INPUT/OUTPUT
DESCRIPTION
Power
For internal logic circuit (+5V±10%)
GND (0V)
For LCD driver circuit
Power
VSS=0V, VDD=5V¡¾10% VDD-VEE=8V~17V
VEE1 and VEE2 is connected by the same voltage.
Bias supply voltage terminals to drive the LCD.
Select Level
V0L(R), V5L(R)
Non-Select Level
V2L(R), V3L(R)
92
91
90
2
1
100
99
98
97
96
95
94
79~86
CS1B
CS2B
CS3
M
ADC
FRM
E
CLK1
CLK2
CL
RS
R/W
DB0~DB7
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/Output
Chip selection
In order to interface data for input or output
The terminals have to be CS1B=L, CS2B=L, and CS3=H.
Alternating signal input for LCD driving.
Address control signal of Y address counter.
ADC=H→DB<0:7>=0→Y0→S1
DB<0:7>=63→Y63→S64
ADC=L→DB<0:7>=0→Y63→S64
DB<0:7>=63→Y0→S1
Synchronous control signal.
Presets the 6-bit Z counter and syncronizes the common signal with the
frame signal when the frame signal becomes high.
Enable signal.
write mode (R/W=L) → data of DB<0:7> is latched at
the falling edge of E.
read mode (R/W=H) → DB<0:7> appears the reading
data while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display
RAM data and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and increments the
Z-address counter at the CL falling time.
Data or Instruction.
RS=H→DB<0:7> : Display RAM Data
RS=L→DB<0:7> : Instruction Data
Read or Write.
R/W=H → Data appears at DB<0:7> and can be read
by the CPU while E=H, CS1B=L, CS2B=L
and CS3=H.
R/W=L¡æDisplay data DB<0:7> can be written at falling of E
when CS1B=L, CS2B=L and CS3=H.
Data bus.
There state I/O common terminal.
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