KS0123 查看數據表（PDF） - Samsung

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KS0123

DIGITAL VIDEO ENCODER

Samsung 

KS0123 Data Sheet

MULTIMEDIA VIDEO

GENERAL DESCRIPTION

The encoder accepts 27 MHz 8-bit multiplexed digital component video in CCIR 656 CbYCr format at the Pixel

Data (PD) port. The pixel data are demultiplexed into luminance and chrominance components for interpolation

and low pass filtering to reduce cross luma/chroma interference. The filtered chrominance signals are modulated

onto a color subcarrier and added to the processed luminance components to form the composite video (CVBS).

The digital CVBS and S-Video signals are interpolated to 27 MHz rate and then converted to analog forms by 3 10-

bit D/A converters.

Anti-taping pulses, synch signals and color burst are generated internally. The rise and fall times of those pulses

are controlled to reduce ringing. The shaped signals are inserted into the video stream controlled by the timing

generator.

The encoder also contains a color subcarrier PLL, which when enabled will frequency and phase lock the color

subcarrier to an external analog fsc or 4 x fsc reference. The SCH phase can be adjusted to compensate for

additional external phase delay.

VIDEO DATA INPUT

PD[7:0]

PXCK

HSYN

FIELD

SDA

HOST SCL

INTERFACE SA1

SA2

RESET

GENERAL PURPOSE

PORT

D[7:0]

GENLOCK SC_REF

INPUT

SC_SYNC

PAL_ID

DIGITAL

VIDEO

ENCODER

VIDEO OUTPUTS

CVBS

Y

C

ANALOG INTERFACE

VREF

BYPASS

RREF

JTAG TEST INTERFACE

TDI

TMS

TCK

TDO

Figure 2. Logic Diagram

Modified on May/04/2000

PAGE 6 OF 44

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