KS0127 查看數據表（PDF） - Samsung

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KS0127

MULTISTANDARD VIDEO DECODER/SCALER

Samsung 

KS0127B Data Sheet

MULTIMEDIA VIDEO

When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional.

If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no

effect. An example of horizontal timing for digital input is shown in Figure 4.

HS1

Programmable, when an

output - Any input phase

is acceptable

This HS1 location can also come

From a 656 SAV code

Constant to internal counter reference

EXV[7:0]

80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux Yx Vx Yx Vx

Data group delay through chip --

Y[7:0]

Y output for OFMT=2 is

shown, any 8 or 16 bit

output format is allowed.

80 10 80 10 80 10 U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4 Y4 V4 Y5 U6 Y6 V6 Y7 Ux Yx Vx Yx Ux

Fully programmable HAVB location

based on internal counter

HAV -- fully programmable,

Defines location of first, last pixel

and defines Cb,Y,Cr data location

Fully programmable

HAVE location

HAV

CK

CK2

CK can be input or output

The CK2 output clock phasing

is aligned to the HAV leading

edge

Figure 4. Horizontal Timing for EXV Port as Digital Input

1.1.5. Additional Information for Analog Component Video Input

For the KS0127B to correctly set the V component phase in analog component video input mode, PID (pin 17) and

PORTA (pin 58) need to be connected together. PORTA has to be configured as input (DIRA = 0) and connected

to the internal CBG signal (DATAA[2:0] = 3).

It is also recommended that external clamp circuit be used for Cb and Cr inputs (before the coupling caps) and the

internal chroma clamp be disabled (COFFENB = 1) due to slight Cb/Cr leakage.

ELECTRONICS

Modified on May/04/2000

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