SAA7165WP 查看數據表（PDF） - Philips Electronics
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SAA7165WP Datasheet PDF : 28 Pages
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Philips Semiconductors
Video Enhancement and Digital-to-Analog
processor (VEDA2)
Product specification
SAA7165
FUNCTIONAL DESCRIPTION
The CMOS circuit SAA7165 processes digital YUV-bus
data up to a data rate of 36 MHz. The data inputs Y7 to Y0
and UV7 to UV0 (see Fig.1) are provided with 8-bit data.
The data of digital colour-difference signals U and V are in
a multiplexed state (serial in 4 : 2 : 2 or 4 : 1 : 1 format;
Tables 2 and 3).
Data is read with the rising edge of LLC (Line-Locked
Clock) to achieve a data rate of LLC at MC = HIGH only. If
MC is supplied with the frequency CREF (1⁄2LLC for
example), data is read only at every second rising edge
(see Fig.3).
The 7-bit YUV input data are also supported by means of
bit R78 (R78 = 0). Additionally, the luminance data format
is converted for internal use into a two´s complement
format by inverting the MSB. The Y input byte
(bits Y7 to Y0) represents luminance information; the UV
input byte (bits UV7 to UV0) represents one of the two
digital colour-difference signals in 4 : 2 : 2 format
(Table 2).
The HREF input signal (HREF = HIGH) determines the
start and the end of an active line (see Fig.3) and the
number of pixels respectively. The analog output Y is
blanked at HREF = LOW, the (B − Y) and (R − Y) outputs
are in a colourless state. The blanking level can be set with
bit BLV. The SAA7165 is controllable via the I2C-bus.
Formatting Y and UV
The input data formats are formatted into the internally
used processing formats (separate for 4 : 2 : 2 and
4 : 1 : 1 formats). The IFF, IFC and IFL bits control the
input data format and determine the right interpolation filter
(see Figs 10 to 13).
Peaking and coring
Peaking is applied to the Y signal to compensate several
bandwidth reductions of the external pre-processing.
Y signals can be improved to obtain a better sharpness.
There are the two switchable bandpass filters
BF1 and BF2 controlled via the I2C-bus by the bits BP1,
BP0 and BFB. Thus, a frequency response is achieved in
combination with the peaking factor K (Figs 5 to 9;
K is determined by the bits BFB, WG1 and WG0).
The coring stage with controllable threshold (4 states
controlled by CO1 and CO0 bits) reduces noise
disturbances (generated by the bandpass gain) by
suppressing the amplitude of small high-frequent signal
components. The remaining high-frequent peaking
component is available for a weighted addition after
coring.
Table 1 LLC and MC configuration modes in DMSD applications (note 1)
PIN
LLC
MC
LLC
MC
LLC
MC
INPUT SIGNAL
LLC (LL27)
CREF
LLC (LL27)
MC = HIGH
LLC (LL27)
MC = HIGH
DESCRIPTION
The data rate on YUV-bus is half the clock rate on pin LLC, e.g. in
SAA7151B, SAA7191 and SAA7191B single scan operation.
The data rate on YUV-bus must be identical to the clock rate on pin LLC,
e.g. in double scan applications.
The data rate on YUV-bus must be identical to the clock rate on pin LLC,
e.g. SAA9051 single scan operation.
Note
1. YUV data are only latched with the rising edge of LCC at MC = HIGH.
1996 Aug 20
6
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