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LC863096 查看數據表(PDF) - SANYO -> Panasonic

零件编号
产品描述 (功能)
比赛名单
LC863096
SANYO
SANYO -> Panasonic SANYO
LC863096 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC863232/28/24/20/16A
- Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.
(15) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(16) Multiplication/division instruction
- 16 bits × 8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(17) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X’tal oscillation circuit used for base timer, system clock and PLL reference
(18) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
Pull the reset terminal ( RES ) to low level.
Feed the selected level to either P70/INT0 or P71/INT1.
Input the interrupt condition to Port 0.
(19) Package
- DIP42S
- QIP48E
(20) Development tools
- Flash EEPROM:
- Evaluation chip:
- Emulator:
LC86F3248A
LC863096
EVA86000 (main) + ECB863200 (evaluation chip board)
+ POD863200 (pod: DIP42S) or POD863201 (QIP48E)
No.6693-4/20

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