LC863524A 查看數據表（PDF） - SANYO -> Panasonic
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LC863524A Datasheet PDF : 19 Pages
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LC863532A/28A/24A/20A/16A
4. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter
Symbol
Standard
min.
max.
High speed
unit
min.
max.
SCL Frequency
fSCL
0
100
0
400 kHz
BUS free time between stop - start
HOLD time of start, restart condition
L time of SCL
tBUF
4.7
-
1.3
-
µs
tHD;STA
4.0
-
0.6
-
µs
tLOW
4.7
-
1.3
-
µs
H time of SCL
Set-up time of restart condition
HOLD time of SDA
Set-up time of SDA
tHIGH
4.0
-
0.6
-
µs
tSU;STA
4.7
-
0.6
-
µs
tHD;DAT
0
-
0
0.9
µs
tSU;DAT
250
-
100
-
ns
Rising time of SDA, SCL
tR
-
1000 20+0.1Cb 300
ns
Falling time of SDA, SCL
tF
-
300 20+0.1Cb 300
ns
Set-up time of stop condition
tSU;STO
4.0
-
0.6
-
µs
Refer to figure 7
(Note) Cb : Total capacitance of all BUS (unit : pF)
5. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V
Parameter Symbol
Pins
Conditions
VDD[V]
Ratings
min. typ. max.
unit
High/low level tPIH(1) •INT0, INT1
pulse width tPIL(1) •INT2/T0IN
•Interrupt acceptable 4.5 to 5.5 1
•Timer0-countable
tCYC
tPIH(2) INT3/T0IN
•Interrupt acceptable 4.5 to 5.5 2
tPIL(2) (1 tCYC is
•Timer0-countable
selected for noise
rejection clock.)
tPIH(3) INT3/T0IN
•Interrupt acceptable 4.5 to 5.5 32
tPIL(3) (16 tCYC is
•Timer0-countable
selected for noise
rejection clock.)
tPIH(4) INT3/T0IN
•Interrupt acceptable 4.5 to 5.5 128
tPIL(4) (64 tCYC is
•Timer0-countable
selected for noise
rejection clock.)
tPIL(5) RES
Reset acceptable
4.5 to 5.5 200
µs
tPIH(6) HS , VS
tPIL(6)
•Display position
4.5 to 5.5 8
controllable (Note)
•The active edge of
HS and VS must
Rising/falling tTHL
HS
time
tTLH
be apart at least
1 tCYC.
•Refer to figure 6.
Refer to figure 6.
4.5 to 5.5
500 ns
No.6844-12/19
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