LIS3DSH 查看數據表（PDF） - STMicroelectronics

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产品描述 (功能)

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LIS3DSH

MEMS digital output motion sensor ultra low-power high performance three-axis “nano” accelerometer

STMicroelectronics 

Digital interfaces

LIS3DSH

Table 13. Transfer when master is writing multiple bytes to slave:

Master ST SAD + W

SUB

DATA

DATA

SP

Slave

SAK

SAK

SAK

SAK

Table 14. Transfer when master is receiving (reading) one byte of data from slave:

Master ST SAD + W

SUB

SR SAD + R

NMAK SP

Slave

SAK

SAK

SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

MAK

NMAK SP

Slave

SAK

SAK

SAK DATA

DATA

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be left HIGH by

the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In the presented communication format, MAK is Master acknowledge and NMAK is No

Master Acknowledge.

6.2

SPI bus interface

The LIS3DSH SPI is a bus slave. The SPI allows to write and read the registers of the

device.

The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

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Doc ID 022405 Rev 1

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