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LIS3DSH 查看數據表(PDF) - STMicroelectronics

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LIS3DSH Datasheet PDF : 53 Pages
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LIS3DSH
Register description
Table 58. FIFO_SRC register description
WTM
Watermark status.
0=FIFO filling is lower than WTM level; 1=FIFO filling is equal or higher than WTM
level
OVRN_FIFO
Overrun bit status. 0=FIFO is not completely filled; 1=FIFO is completely filled
EMPTY
FIFO empty bit.
0=FIFO not empty; 1=FIFO empty)
FSS4-FSS0
FIFO stored data level
8.28
CTRL_REG1 (21h)
SM1 control register.
Table 59. SM1 control register
HYST2_1 HYST1_1 HYST0_1
-
SM1_PIN
-
-
SM1_EN
Table 60.
HYST2_1
HYST1_1
HYST0_1
SM1_PIN
SM1_EN
SM1 control register structure
Hysteresis unsigned value to be added or subtracted from threshold value in SM1
Default value=000
0=SM1 interrupt routed to INT1, 1=SM1 interrupt routed to INT2 pin
Default value=0
0=SM1 disabled, 1=SM1 enabled
Default value=0
8.29
STx_1 (40h-4Fh)
State machine 1 code register STx_1 (x = 1-16).
State machine 1 system register is made up of 16, 8- bit registers to implement 16-step op-
code.
8.30
TIM4_1 (50h)
8-bit general timer (unsigned value) for SM1 operation timing.
Table 61. Timer4 default value
0
0
0
0
0
0
0
0
8.31
TIM3_1 (51h)
8-bit general timer (unsigned value) for SM1 operation timing.
Doc ID 022405 Rev 1
41/53

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