LM3S2965 查看數據表（PDF） - Unspecified
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LM3S2965 Datasheet PDF : 574 Pages
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LM3S2965 Microcontroller
10 General-Purpose Timers ................................................................................................. 205
10.1 Block Diagram ........................................................................................................................ 205
10.2 Functional Description ............................................................................................................. 206
10.2.1 GPTM Reset Conditions .......................................................................................................... 207
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 207
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 208
10.3 Initialization and Configuration ................................................................................................. 212
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 213
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 213
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 214
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 214
10.3.6 16-Bit PWM Mode ................................................................................................................... 215
10.4 Register Map .......................................................................................................................... 215
10.5 Register Descriptions .............................................................................................................. 216
11 Watchdog Timer ............................................................................................................... 241
11.1 Block Diagram ........................................................................................................................ 241
11.2 Functional Description ............................................................................................................. 241
11.3 Initialization and Configuration ................................................................................................. 242
11.4 Register Map .......................................................................................................................... 242
11.5 Register Descriptions .............................................................................................................. 243
12 Analog-to-Digital Converter (ADC) ................................................................................. 264
12.1 Block Diagram ........................................................................................................................ 265
12.2 Functional Description ............................................................................................................. 265
12.2.1 Sample Sequencers ................................................................................................................ 265
12.2.2 Module Control ........................................................................................................................ 266
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 267
12.2.4 Analog-to-Digital Converter ...................................................................................................... 267
12.2.5 Test Modes ............................................................................................................................. 267
12.2.6 Internal Temperature Sensor .................................................................................................... 267
12.3 Initialization and Configuration ................................................................................................. 268
12.3.1 Module Initialization ................................................................................................................. 268
12.3.2 Sample Sequencer Configuration ............................................................................................. 268
12.4 Register Map .......................................................................................................................... 269
12.5 Register Descriptions .............................................................................................................. 270
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 297
13.1 Block Diagram ........................................................................................................................ 298
13.2 Functional Description ............................................................................................................. 298
13.2.1 Transmit/Receive Logic ........................................................................................................... 298
13.2.2 Baud-Rate Generation ............................................................................................................. 299
13.2.3 Data Transmission .................................................................................................................. 300
13.2.4 Serial IR (SIR) ......................................................................................................................... 300
13.2.5 FIFO Operation ....................................................................................................................... 301
13.2.6 Interrupts ................................................................................................................................ 301
13.2.7 Loopback Operation ................................................................................................................ 302
13.2.8 IrDA SIR block ........................................................................................................................ 302
13.3 Initialization and Configuration ................................................................................................. 302
13.4 Register Map .......................................................................................................................... 303
November 30, 2007
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