PCK2510S 查看數據表（PDF） - Philips Electronics
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PCK2510S Datasheet PDF : 10 Pages
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Philips Semiconductors
50–150 MHz 1:10 SDRAM clock driver
Product specification
PCK2510S
RECOMMENDED OPERATING CONDITIONS1
SYMBOL
PARAMETER
CONDITIONS
VCC, AVCC Supply voltage
VIH
HIGH level input voltage
VIL
LOW level input voltage
VI
Input voltage
Tamb
Operating ambient temperature range in free air
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
VIK
Input clamp voltage
VOH
HIGH level output voltage
VOL
LOW level output voltage
II
ICC
ICCA
∆ICC
CI
CO
Input current
Quiescent supply current
AVCC power supply current
Additional supply current per
input pin
Input capacitance
Output capacitance
TEST CONDITIONS
AVCC, VCC (V)
3
MIN to MAX
3
3
MIN to MAX
3
3
3.6
3.6
AVCC = 3.3
3.3 to 3.6
3.3
3.3
OTHER
II = –18 mA
IOH = – 100 µA
IOH = – 12 mA
IOH = – 6 mA
IOL = 100 µA
IOL = 12 mA
IOL = 6 mA
VI = VCC or GND
VI = VCC or GND;
IO = 0, outputs: LOW or HIGH
One input at VCC – 0.6 V;
other inputs at VCC or GND
VI = VCC or GND
VO= VCC or GND
LIMITS
MIN
MAX
3
3.6
2
0
0.8
0
VCC
0
+70
UNIT
V
V
V
V
°C
LIMITS
MIN
TYP
VCC – 0.2
2.1
2.4
–
–
–
30
2.8
5.4
MAX
–1.2
0.2
0.8
0.55
±5
10
50
500
UNIT
V
V
V
µA
µA
µA
µA
pF
pF
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature
SYMBOL
PARAMETER
MIN
MAX
UNIT
fCLK Clock frequency
Input clock duty cycle
Stabilization time1
50
150
MHz
40
60
%
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
1999 Dec 13
5
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