LP61L1024 查看數據表（PDF） - AMIC Technology

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LP61L1024

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

AMIC Technology 

Truth Table

Mode

Standby

Output Disable

Read

Write

Note: X = H or L

CE1

CE2

OE

WE

H

X

X

X

X

L

X

X

L

H

H

H

L

H

L

H

L

H

X

L

I/O Operation

High Z

High Z

High Z

DOUT

DIN

LP61L1024

Supply Current

ISB, ISB1

ISB, ISB2

ICC1

ICC1

ICC1

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol

CIN*

CI/O*

Parameter

Min.

Max.

Unit

Input Capacitance

8

pF

Input/Output Capacitance

10

pF

* These parameters are sampled and not 100% tested.

Conditions

VIN = 0V

VI/O = 0V

AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V)

Symbol

Parameter

Read Cycle

tRC

Read Cycle Time

tAA

Address Access Time

tACE1 Chip Enable Access Time

tACE2

tOE

tCLZ1

Output Enable to Output Valid

Chip Enable to Output in Low Z

tCLZ2

tOLZ

tCHZ1

Output Enable to Output in Low Z

Chip Disable to Output in High Z

tCHZ2

tOHZ

tOH

Output Disable to Output in High Z

Output Hold from Address Change

CE1

CE2

CE1

CE2

CE1

CE2

LP61L1024-12

Min.

Max.

12

-

-

12

-

12

-

12

-

7

3

-

3

-

2

-

-

7

-

7

2

7

3

-

LP61L1024-15

Min.

Max.

15

-

-

15

-

15

-

15

-

9

5

-

5

-

2

-

-

10

-

10

2

9

5

-

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

(August, 2004, Version 2.2)

4

AMIC Technology, Corp.

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