LP621024D-55LLI 查看數據表（PDF） - AMIC Technology

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LP621024D-55LLI

128K X 8 BIT CMOS SRAM

AMIC Technology 

Block Diagram

A0

A14

A15

A16

I/O1

I/O8

ROW

DECODER

LP621024D-I Series

512 X 2048

MEMORY ARRAY

VCC

GND

INPUT DATA

CIRCUIT

COLUMN I/O

CE2

CE1

CONTROL

OE

CIRCUIT

WE

Pin Descriptions - DIP/SOP

Pin No.

Symbol

Description

1

NC

No Connection

2 - 12, 23,

25 - 28, 31

A0 - A16

Address Inputs

13 - 15,

17 - 21

I/O1 - I/O8

Data Input/Outputs

16

GND

Ground

22

CE1

Chip Enable

24

OE

Output Enable

29

WE

Write Enable

30

CE2

Chip Enable

32

VCC

Power Supply (+5V)

Pin Description - TSOP/TSSOP

Pin No.

Symbol

Description

1 - 4, 7,

10 - 20, 31

A0 - A16

Address Inputs

5

WE

Write Enable

6

CE2

Chip Enable

8

VCC

Power Supply

9

NC

No Connection

21 - 23,

25 - 29

I/O1 - I/O8

Data Input/Outputs

24

GND

Ground

30

CE1

Chip Enable

32

OE

Output Enable

PRELIMINARY (August, 2002, Version 0.0)

3

AMIC Technology, Inc.

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