LP62E16512-T(2002) 查看數據表（PDF） - AMIC Technology

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LP62E16512-T
(Rev.:2002)

512K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

LP62E16512-T Series

0.2V to VCC-0.2V

5 ns

0.8V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ ,

tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW

Symbol

Parameter

Min. Max. Unit

Conditions

VDR

VCC for Data Retention

1.2

2.2

ICCDR

Data Retention Current

-

0.2*

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

tRC

-

VCC Rising Time from Data Retention

tVR

Voltage to Operating Voltage

5

-

* LP62E16512 - 70LLT

ICCDR: max. 0.1µA at TA = 25°C

(0.2µA at TA = 0°C to + 40°C )

CS1 ≥ VCC - 0.2V or

V

CS2 ≤ 0.2V or

LB = HB ≥ VCC-0.2V

VCC = 1.2V,

CS1 ≥ VCC - 0.2V or

µA

CS2 ≤ 0.2V or

LB = HB ≥ VCC-0.2V

VIN ≥ VCC-0.2V or VIN ≤ 0.2V

ns

ns See Retention Waveform

ms

PRELIMINARY (April, 2002, Version 0.0)

11

AMIC Technology, Inc.

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