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LT1681

Dual Transistor Synchronous Forward Controller

Linear Technology 

LT1681

APPLICATIO S I FOR ATIO

to the minimum off time, the converter maximum duty

cycle can be forced using the SYNC input. For example, a

30% duty cycle SYNC pulse forces 30% maximum duty

cycle operation for the converter. Because the logic low

pulse width exceeds the logic high pulse width in < 50%

duty cycle operation, the oscillator free-run cycle time

must be programmed to exceed the logic low duration.

2.5V

FSET

1.5V

SYNC

SYSTEM

CLOCK

(INTERNAL)

1681 F04

Figure 4. Oscillator/SYNC Waveforms

It is also possible to run the LT1681 in a SYNC-only mode

by disabling the oscillator completely. Connecting a resis-

tor divider from the 5VREF pin to the FSET pin, forcing a

voltage within the charge range of 1.5V to 2.5V, will allow

the oscillator to follow the SYNC input exclusively with no

provision for free-run. Setting values to force a voltage as

close to 2V as possible is recommended.

5 5VREF

75k

LT1681

6 FSET

50k

100pF

1681 F05

Figure 5. Oscillator Connection for Sync-Only Mode Operation

Shutdown

The LT1681 SHDN pin will support TTL and CMOS logic

signals and also analog inputs. The SHDN pin turn-on

(rising) threshold is 1.25V with 150mV of hysteresis. A

common use of the SHDN pin is for undervoltage detec-

tion on the input supply. Driving the SHDN pin with a

resistor divider connected from the input supply to ground

will prevent switching until the desired input supply volt-

age is achieved.

The LT1681 enters an ultralow current shutdown mode

when the SHDN pin is below 350mV. During this mode,

total supply current drops to a typical value of less than

1µA. When SHDN rises above 350mV, the IC will draw

increasing amounts of supply current until just before the

1.25V turn-on threshold is achieved, when the typical

supply current reaches 60µA.

The shutdown function can be disabled by connecting the

SHDN pin to VCC. This pin is internally clamped to 2.5V

through a 20k series input resistance and can therefore

draw almost 1mA when tied directly to the VCC supply. This

additional current can be minimized by making the con-

nection through an external series resistor (100k is typi-

cally used).

Soft-Start

The LT1681 current control pin (VC) limits sensed current

to zero at voltages less than 1.4V through full current limit

at VC = 3.2V, yielding 1.8V over the full regulation range.

The voltage on the VC pin is internally forced to be less than

or equal to SS + 0.7V. As such, the SS pin has a “dead

zone” between 0V and 0.7V, where a zero sensed current

condition is maintained. At SS voltages above 0.7V, the

sensed current limit threshold on pin VC may rise as

needed up to the SS maintained current limit value. Once

the SS pin rises to the VC pin maximum value less 0.7V, or

2.5V, the SS circuit has no effect.

The SS pin sources a typical current of 10µA. Placing a

capacitor (CSS) from the SS pin to ground will cause the

voltage on the SS pin to ramp up at a controlled rate,

allowing a graceful increase of maximum converter output

current during a start-up condition. The start-up delay

time to full available current limit is:

tSS = 2.5 • 105 • CSS (sec)

The LT1681 internally pulls the SS pin below the zero

current threshold during any fault condition to assure

graceful recovery. The SS circuit also acts as a fault control

latch to assure a full-range recovery from a short duration

fault. Once a fault condition is detected, the LT1681 will

suspend switching until the SS pin has discharged to

approximately 225mV.

1681f

13

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