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LTC1250
(Rev.:RevA)

Very Low Noise Zero-Drift Bridge Amplifier

Linear Technology 

LTC1250

APPLICATI S I FOR ATIO

Output Drive

The LTC1250 includes an enhanced output stage which

provides nearly symmetrical output source/sink currents.

This output is capable of swinging a minimum of ±4V into a

1k load with ±5V supplies, and can sink or source >20mA

into low impedance loads. Lightly loaded (RL ≥100k), the

LTC1250 will swing to within millivolts of either rail. In single

supply applications, it will typically swing 4.3V into a 1k load

with a 5V supply.

Minimizing External Errors

The input noise, offset voltage, and bias current specs for the

LTC1250 are all well below the levels of circuit board

parasitics. Thermocouples between the copper pins of the

LTC1250 and the tin/lead solder used to connect them can

overwhelm the offset voltage of the LTC1250, especially if a

soldering iron has been around recently. Note also that when

the LTC1250’s output is heavily loaded, the chip may

dissipate substantial power, raising the temperature of the

package and aggravating thermocouples at the inputs.

Although the LTC1250 will maintain its specified accuracy

under these conditions, care must be taken in the layout to

prevent or compensate circuit errors. Be especially careful

of air currents when measuring low frequency noise; nearby

moving objects (like people) can create very large noise

peaks with an unshielded circuit board. For more detailed

explanations and advice on how to avoid these errors, see

the LTC1051/LTC1053 data sheet.

Sampling Behavior

The LTC1250’s zero-drift nulling loop samples the input at

≈ 5kHz, allowing it to process signals below 2kHz with no

aliasing. Signals above this frequency may show aliasing

behavior, although wideband internal circuitry generally

keeps errors to a minimum. The output of the LTC1250 will

have small spikes at the clock frequency and its harmonics;

these will vary in amplitude with different feedback configu-

rations. Low frequency or band-limited systems should not

be affected, but systems with higher bandwidth

(oversampling A/Ds, for example) may need to filter out

these clock artifacts. Output spikes can be minimized with a

large feedback capacitor, but this will adversely affect noise

performance (see Input Capacitance and Compensation on

the previous page). Applications which require spike-free

output in addition to minimum noise will need a low-pass

filter after the LTC1250; a simple RC will usually do the job

(Figure 4). The LTC1051/LTC1053 data sheet includes more

information about zero-drift amplifier sampling behavior.

CF

RF

–

LTC1250

+

47k

0.01

1250 F04

Figure 4. RC Output Pole Limits Bandwidth to 330Hz

Single Supply Operation

The LTC1250 will operate with single supply voltages as low

as 4.5V, and the output swings to within millivolts of either

supply when lightly loaded. The input stage will common

mode to within 250mV of ground with a single 5V supply,

and will common mode to ground with single supplies

above 11V. Most bridge transducers bias their inputs above

ground when powered from single supplies, allowing them

to interface directly to the LTC1250 in single supply applica-

tions. Single-ended, ground-referenced signals will need to

be level shifted slightly to interface to the LTC1250’s inputs.

Fault Conditions

The LTC1250 is designed to withstand most external fault

conditions without latch-up or damage. However, unusually

severe fault conditions can destroy the part. All pins are

protected against faults of ±25mA or 5V beyond either

supply, whichever comes first. If the external circuitry can

exceed these limits, series resistors or voltage clamp diodes

should be included to prevent damage.

The LTC1250 includes internal protection against ESD dam-

age. All data sheet parameters are maintained to 1kV ESD on

any pin; beyond 1kV, the input bias and offset currents will

increase, but the remaining specs are unaffected and the

part remains functional to 5kV at the input pins and 8kV at the

output pin. Extreme ESD conditions should be guarded

against by using standard anti-static precautions.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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