LTC6102HVCDD(RevB) 查看數據表（PDF） - Linear Technology
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LTC6102HVCDD Datasheet PDF : 20 Pages
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LTC6102/LTC6102HV
TYPICAL PERFORMANCE CHARACTERISTICS
Step Response Rising Edge
Step Response Falling Edge
PSRR vs Frequency
160
VSENSE– = 100mV
5.5V
5V
0.5V VOUT
0V
IOUT = 0
IOUT = 100μA
TVA+
=
=
25°C
12V
RIN = 100Ω
VRSOEUNTS=E+4=.9V9k+
TIME (500ns/DIV)
6102 G17
VSENSE– = 100mV
5.5V
5V
VOUT
TVA+
=
=
25°C
12V
RIN = 100Ω
RVSOEUNTS=E+4=.9V9k+
IOUT = 100μA
IOUT = 0
0.5V
0V
TIME (500ns/DIV)
6102 G18
140
120
100
80
60 V+ = 12V
RIN = 100Ω
40
ROUT = 4.99k
AV = 49.9
IOUT = 500μA
20
0.1 1 10 100 1k 10k
FREQUENCY (Hz)
100k 1M
6102 G19
Input Referred Noise
0.1Hz to 10Hz
5
4
TVA+
=
=
25°C
12V
3
RIN = 10Ω
ROUT = 1k
2 VSENSE = 2mV
Noise Spectral Density
2
1
0
1
–1
–2
–3
–4
–5
0 1 2 3 4 5 6 7 8 9 10
TIME (s)
6102 G20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
6102 G21
PIN FUNCTIONS
–INS (Pin 1): Amplifier Inverting Input. When tied to –INF,
the internal sense amplifier will drive –INS to the same
potential as +IN.
–INF (Pin 2): Force Input. This pin carries the input
current from RIN and must be tied to –INS near RIN. A
resistor (RIN) tied from V+ to –INF sets the output current
IOUT = VSENSE/RIN. VSENSE is the voltage across the ex-
ternal RSENSE.
V– (Pins 3, 5): Negative Supply.
OUT (Pin 4): Open-Drain Current output. OUT will source a
current that is proportional to the sense voltage into an ex-
ternal resistor. IOUT is the same current that enters –INF.
VREG (Pin 6): Internal Regulated Supply. A 0.1μF (or
larger) capacitor should be tied from VREG to V+. VREG is
not designed to drive external circuits.
V+ (Pin 7): Positive Supply. Supply current is drawn
through this pin.
+IN (Pin 8): Amplifier Non-Inverting Input. Must be tied
to the system load end of the sense resistor.
Exposed Pad (Pin 9, DFN Only): V–. The Exposed Pad
must be soldered to PCB.
6102fb
7
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