IDT7MB4048S35P 查看數據表（PDF） - Integrated Device Technology
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IDT7MB4048S35P Datasheet PDF : 6 Pages
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IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
2675 tbl 09
+5 V
DATAOUT
255Ω
480 Ω
30 pF*
COMMERCIAL TEMPERATURE RANGE
DATAOUT
255Ω
+5 V
480 Ω
5 pF*
Figure 1. Output Load
2675 drw 04
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol
Read Cycle
Parameter
tRC
Read Cycle Time
tAA
Address Access Time
tACS Chip Select Access Time
tOE
tOHZ(1)
tOLZ(1)
tCLZ(1)
tCHZ(1)
Output Enable to Output Valid
Output Disable to Output in High-Z
Output Enable to Output in Low-Z
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
tOH
tPU(1)
tPD(1)
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle
tWC Write Cycle Time
tWP
tAS(2)
Write Pulse Width
Address Set-up Time
tAW Address Valid to End-of-Write
tCW Chip Select to End-of-Write
tDW
tDH(2)
tWR(2)
tWHZ(1)
tOW(1)
Data to Write Time Overlap
Data Hold Time
Write Recovery Time
Write Enable to Output in High-Z
Output Active from End-of-Write
NOTES
1. This parameter is guaranteed by design, but not tested.
2. tAS=0ns for CS controlled write cycles. tDH, tWR= 3ns for CS controlled write cycles.
7.11
2675 drw 05
Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, tWHZ, tOW and tCLZ)
7MB4048
–25
–30
–35
Min. Max. Min. Max. Min. Max. Unit
25 — 30 — 35 — ns
— 25 — 30 — 35 ns
— 25 — 30 — 35 ns
— 12 — 15 — 15 ns
— 12 — 12 — 15 ns
0—
0
— 0 — ns
5—
5
— 5 — ns
— 14 — 16 — 20 ns
3—
3
— 3 — ns
0—
0
— 0 — ns
— 25 — 30 — 35 ns
25 — 30 — 35 — ns
17 — 20 — 25 — ns
3—
0
— 0 — ns
20 — 25 — 30 — ns
20 — 25 — 30 — ns
15 — 17 — 20 — ns
0—
0
— 0 — ns
0—
0
— 0 — ns
— 15 — 15 — 15 ns
2—
5
— 5 — ns
2675 tbl 10
3
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