M27V102 查看數據表（PDF） - STMicroelectronics
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M27V102 Datasheet PDF : 15 Pages
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M27V102
Table 5. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
High Speed
≤ 10ns
0 to 3V
1.5V
Standard
≤ 20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
0V
Standard
2.4V
0.4V
1.5V
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
CL
OUT
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
COUT
Output Capacitance
Note: 1. Sampled only, not 100% tested.
VIN = 0V
VOUT = 0V
6
pF
12
pF
For the most efficient use of thesetwo control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselectedmem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer :
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transientcurrent peaks is dependenton the capaci-
tive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between Vcc and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
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