M2V64S20DTP 查看數據表（PDF） - Mitsumi

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M2V64S20DTP

64M Synchronous DRAM

Mitsumi 

MITSUBISHI LSIs

SDRAM (Rev.3.2)

Feb.'00

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)

64M Synchronous DRAM

COMMAND TRUTH TABLE

COMMAND

MNEMONIC CKE CKE /CS /RAS /CAS /WE BA0,1 A11 A10 A0-9

n-1 n

Deselect

DESEL

H XHX XX X XXX

No Operation

Row Address Entry &

Bank Activate

Single Bank Precharge

NOP

ACT

PRE

H X L HHH X X X X

H X L L HH V V V V

HX L L HL V X LX

Precharge All Banks

Column Address Entry

& Write

Column Address Entry &

Write with Auto-Precharge

Column Address Entry

& Read

Column Address Entry &

Read with Auto-Precharge

Auto-Refresh

PREA

WRIT E

WRITEA

READ

READA

REFA

HX L L HL X

HXLHLL V

HXLHLL V

HXLHLHV

HXLHLHV

HHLL LHX

XHX

VLV

VHV

VLV

VHV

XXX

Self-Refresh Entry

REFS

HL LL LHXXXX

Self-Refresh Exit

REFSX

L HHX XX X XXX

L HL HHH X X X X

Burst Terminate

TBST

HX

L

HHL

XX

XX

Mode Register Set

MRS

H X L L L L L L L V*1

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-A9 =0, A0-A6 =Mode Address

MITSUBISHI ELECTRIC

6

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