P4C1024L-70PI 查看數據表（PDF） - Performance Semiconductor

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P4C1024L-70PI

LOW POWER 128K x 8 CMOS STATIC RAM

Performance Semiconductor 

P4C1024L

READ CYCLE NO. 1 (OE CONTROLLED)(1)

ADDRESS

OE

CE

CE2

DATA OUT

tAA

tOE

tOLZ

tAC

tLZ

tRC(5)

tOH

tOHZ

tHZ

Notes:

1. WE is HIGH for READ cycle.

2.

CE

1

and

OE

is LOW, and CE2 is HIGH for READ cycle.

3. ADDRESS must be valid prior to, or coincident with later of

CE

1

transition

LOW

or

CE2

transition

HIGH.

4. Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is

sampled and not 100% tested.

5. READ Cycle Time is measured from the last valid address to the

first transitioning address.

READ CYCLE NO. 2 (ADDRESS CONTROLLED)

ADDRESS

DATA OUT

tAA

tOH

PREVIOUS DATA VALID

tRC (5)

DATA VALID

READ CYCLE NO. 3 (CE CONTROLLED)

tRC

CE1

CE2

DATA OUT

ICC

VCC SUPPLY

CURRENT

ISB

tAC

tLZ

tPU

tHZ

DATA VALID

tPD

HIGH IMPEDANCE

154

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