M38C88EA-XXXFP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M38C88EA-XXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer Y

Timer Y is a 16-bit timer that can be selected in one of four modes.

(1) Timer Mode

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

(2) Period Measurement Mode

CNTR1 interrupt request is generated at rising/falling edge of CNTR1

pin input signal. Simultaneously, the value in timer Y latch is reloaded

in timer Y and timer Y continues counting down. Except for the above-

mentioned, the operation in period measurement mode is the same

as in timer mode.

The timer value just before the reloading at rising/falling of CNTR1

pin input signal is retained until the timer Y is read once after the

reload.

The rising/falling timing of CNTR1 pin input signal is found by CNTR1

interrupt. When using a timer in this mode, set the port shared with

the CNTR1 pin to input.

(3) Event Counter Mode

The timer counts signals input through the CNTR1 pin.

Except for this, the operation in event counter mode is the same as

in timer mode. When using a timer in this mode, set the port shared

with the CNTR1 pin to input.

(4) Pulse Width HL Continuously Measurement

Mode

CNTR1 interrupt request is generated at both rising and falling edges

of CNTR1 pin input signal. Except for this, the operation in pulse

width HL continuously measurement mode is the same as in period

measurement mode. When using a timer in this mode, set the port

shared with the CNTR1 pin to input.

sNotes on CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit. However, in the pulse width HL continuously measure-

ment mode, CNTR1 interrupt request is generated at both rising and

falling edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

b7

b0

Timer Y mode register

(TYM : address 002816)

Timer X count source selection bit

0 : f(XIN)/16 (f(XCIN)/16 in low-speed mode✽)

1 : f(XIN)

Not used (return “0” when read)

Timer Y operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuously

measurement mode

CNTR1 active edge switch bit

0 : Count at rising edge in event counter mode

Measure the falling edge to falling edge

period in period measurement mode

Interrupt falling edge active

1 : Count at falling edge in event counter mode

Measure the rising edge period in period

measurement mode

Interrupt rising edge active

Timer Y stop control bit

0 : Count start

1 : Count stop

✽ Internal clock φ in low-speed mode is XCIN divided by 2.

When the timer X operating mode bits are “00” or “11”, the timer X count source is

f(XCIN)/16. When the timer X operating mode bits are “01”, the timer X count source

is f(XCIN).

Fig. 18 Structure of timer Y mode register

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