M48Z129V-70PM1(2000) 查看數據表（PDF） - STMicroelectronics
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M48Z129V-70PM1 Datasheet PDF : 13 Pages
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M48Z129Y, M48Z129V
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
–40 to 70
°C
TBIAS
Temperature Under Bias
–10 to 70
°C
TSLD (2)
Lead Solder Temperature for 10 seconds
260
°C
VIO
Input or Output Voltages
–0.3 to VCC+0.3
V
VCC
Supply Voltage
M48Z129Y
M48Z129V
–0.3 to 7.0
–0.3 to 4.6
V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Figure 2A. DIP Pin Connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 M48Z129Y 25
9 M48Z129V 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A15
BL
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02310
DESCRIPTION
The M48Z129Y/V ZEROPOWER SRAM is a
1,048,576 bit non-volatile static RAM organized as
131,072 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a con-
trol circuit in a plastic 32 pin DIP Module. The
M48Z129Y/V directly replaces industry standard
128K x 8 SRAM. It also provides the non-volatility
of FLASH without any requirement for special
write timing or limitations on the number of writes
that can be performed.
The M48Z129Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing data security in
the midst of unpredictable system operation. As
VCC falls, the control circuitry automatically switch-
es to the battery, maintaining data until valid power
is restored.
READ MODE
The M48Z129Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
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