MC80C86 查看數據表（PDF） - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

WAVEFORMS (Continued)

MAXIMUM MODE (Continued)

M80C86 M80C86-2

271058 – 10

NOTES

1 All timing measurements are made at 1 5V

2 RDY is sampled near the end of T2 T3 TW to determine if TW machines states are to be inserted

3 Cascade address is valid between first and second INTA cycle

4 Two INTA cycles run back-to-back The M80C86 local ADDR DATA BUS is floating during both INTA cycles Control for

pointer address is shown for second INTA cycle

5 Signals at M82C84A or M82C88 are shown for reference only

6 The issuance of the M82C88 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and

DEN) lags the active high M82C88 CEN

7 Status inactive in state just prior to T4

17

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