LC75804 查看數據表（PDF） - SANYO -> Panasonic
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LC75804 Datasheet PDF : 37 Pages
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LC75804E, LC75804W
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
DO
DI
CL
CE
VDD
COMMON
DRIVER
CLOCK
GENERATOR
CCB
INTERFACE
VDET
SEGMENT DRIVER & LATCH
SHIFT REGISTER
CONTROL
REGISTER
KEY BUFFER
KEY SCAN
Blocks that are reset
3. Output pin states during the reset period
Output pin
S1/P1 to S8/P8
S9 to S73
COM1 to COM3
COM4/S74
KS1/S75, KS2/S76
KS3 to KS5
KS6
DO
State during reset
L *5
L
L
L *6
L *5
X *7
H
H *8
X: don’t care
Notes:*5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is
transferred, either the common output or the segment output function is selected.
*7. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*8. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
No. 6266-26/37
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