CY7C43684-7AC 查看數據表（PDF） - Cypress Semiconductor

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CY7C43684-7AC

1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644

CY7C43664

CY7C43684

when a read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least two

flip-flop stages. This is done to improve flag-signal reliability by

reducing the probability of the metastable events when CLKA

and CLKB operate asynchronously to one another. EFA/ORA,

AEA, FFA/IRA, and AFA are synchronized to CLKA.

EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to

CLKB. Table 4 and Table 5 show the relationship of each port

flag to FIFO1 and FIFO2.

Empty/Output Ready Flags (EFA/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT Mode, the Output

Ready (ORA, ORB) function is selected. When the Output

Ready flag is HIGH, new data is present in the FIFO output

register. When the Output ready flag is LOW, the previous data

word is present in the FIFO output register and attempted

FIFO reads are ignored. (See footnote #1)

In the CY Standard mode, the Empty Flag (EFA, EFB) function

is selected. When the Empty Flag is HIGH, data is available in

the FIFO’s RAM memory for reading to the output register.

When Empty Flag is LOW, the previous data word is present

in the FIFO output register and attempted FIFO reads are

ignored.

The Empty/Output Ready flag of a FIFO is synchronized to the

port clock that reads data from its array. For both the FWFT

and CY Standard modes, the FIFO read pointer is incremented

each time a new word is clocked to its output register. The

state machine that controls an Output Ready flag monitors a

write pointer and read pointer comparator that indicates when

the FIFO SRAM status is empty, or empty+1.

In FWFT mode, from the time a word is written to a FIFO, it

can be shifted to the FIFO output register in a minimum of

three cycles of the Output Ready flag synchronizing clock.

Therefore, an Output Ready flag is LOW if a word in memory

is the next data to be sent to the FIFO output register and three

cycles have not elapsed since the time the word was written.

The Output Ready flag of the FIFO remains LOW until the third

LOW-to-HIGH transition of the synchronizing clock occurs,

simultaneously forcing the Output Ready flag HIGH and

shifting the word to the FIFO output register.

In the CY Standard mode, from the time a word is written to a

FIFO, the Empty Flag will indicate the presence of data

available for reading in a minimum of two cycles of the Empty

flag synchronizing clock. Therefore, an Empty flag is LOW if a

word in memory is the next data to be sent to the FIFO output

register and two cycles have not elapsed since the time the

word was written. The Empty Flag of the FIFO remains LOW

until the second LOW-to-HIGH transition of the synchronizing

clock occurs, forcing the Empty flag HIGH; only then can data

be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag

synchronizing clock begins the first synchronization cycle of a

write if the clock transition occurs at time tSKEW1 or greater

after the write. Otherwise, the subsequent clock cycle can be

the first synchronization cycle.

Full/Input Ready Flags (FFA/IRA, FFB/IRB)

This is a dual-purpose flag. In FWFT mode, the Input Ready

(IRA and IRB) function is selected. In CY Standard mode, the

Full Flag (FFA and FFB) function is selected. For both timing

modes, when the Full/Input Ready flag is HIGH, a memory

location is free in the SRAM to receive new data. No memory

locations are free when the Full/Input Ready flag is LOW and

attempted writes to the FIFO are ignored.

The Full/Input Ready flag of a FIFO is synchronized to the port

clock that writes data to its array. For both FWFT and CY

Standard modes, each time a word is written to a FIFO, its

write pointer is incremented. The state machine that controls

a Full/Input Ready flag monitors a write pointer and read

pointer comparator that indicates when the FIFO SRAM status

is full, or full–1. From the time a word is read from a FIFO, its

previous memory location is ready to be written to in a

minimum of two cycles of the Full/Input Ready flag synchro-

nizing clock. Therefore, a Full/Input Ready flag is LOW if less

than two cycles of the Full/Input Ready flag synchronizing

clock have elapsed since the next memory write location has

been read. The second LOW-to-HIGH transition on the

Full/Input Ready flag synchronizing clock after the read sets

the Full/Input Ready flag HIGH.

A LOW-to-HIGH transition on a Full/Input Ready flag synchro-

nizing clock begins the first synchronization cycle of a read if

the clock transition occurs at time tSKEW1 or greater after the

read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

Almost Empty Flags (AEA, AEB)

The Almost Empty flag of a FIFO is synchronized to the port

clock that reads data from its array. The state machine that

controls an Almost Empty flag monitors a write pointer and

read pointer comparator that indicates when the FIFO SRAM

status is almost empty, or almost empty+1. The Almost Empty

state is defined by the contents of register X1 for AEB and

register X2 for AEA. These registers are loaded with preset

values during a FIFO reset, programmed from Port A, or

programmed serially (see Almost Empty flag and Almost Full

flag offset programming above). An Almost Empty flag is LOW

when its FIFO contains X or less words and is HIGH when its

FIFO contains (X+1) or more words. [2]

Two LOW-to-HIGH transitions of the Almost Empty flag

synchronizing clock are required after a FIFO write for its

Almost Empty flag to reflect the new level of fill. Therefore, the

Almost Empty flag of a FIFO containing (X+1) or more words

remains LOW if two cycles of its synchronizing clock have not

elapsed since the write that filled the memory to the (X+1)

level. An Almost Empty flag is set HIGH by the second

LOW-to-HIGH transition of its synchronizing clock after the

FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH

transition of an Almost Empty flag synchronizing clock begins

the first synchronization cycle if it occurs at time tSKEW2 or

greater after the write that fills the FIFO to (X+1) words.

Otherwise, the subsequent synchronizing clock cycle may be

the first synchronization cycle.

Almost Full Flags (AFA, AFB)

The Almost Full flag of a FIFO is synchronized to the port clock

that writes data to its array. The state machine that controls an

Almost Full flag monitors a write pointer and read pointer

comparator that indicates when the FIFO SRAM status is

almost full, or almost full–1. The Almost Full state is defined by

the contents of register Y1 for AFA and register Y2 for AFB.

These registers are loaded with preset values during a FIFO

reset, programmed from Port A, or programmed serially (see

Document #: 38-06022 Rev. *B

Page 8 of 39

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