CY7C43686-15AI 查看數據表（PDF） - Cypress Semiconductor

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CY7C43686-15AI

1K/4K/16K x36/x18/x2 Tri Bus FIFO

Cypress Semiconductor 

CY7C43646

CY7C43666

CY7C43686

Pin Definitions (continued)

Signal Name Description I/O

Function

BE/FWFT

Big Endian/

First-Word

Fall-Through

Select

I This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

operation. In this case, depending on the bus size, the most significant byte or word

on Port A is transferred to Port B first for A-to-B data flow. For data flowing from Port

C to Port A, the first word/byte written to Port C will come out as the most significant

word/byte on Port A. On the other hand a LOW on BE will select Little Endian operation.

In this case, the least significant byte or word on Port A is transferred to Port B first for

A to B data flow. Similarly, the first word/byte written into Port C will come out as the

least significant word/byte on Port A for C-to-A data flow. After Master Reset, this pin

selects the timing mode. A HIGH on FWFT selects CY Standard Mode, a LOW selects

First-Word Fall-Through Mode. Once the timing mode has been selected, the level on

this pin must be static throughout device operation.

C0–17

CLKA

Port B Data

Port A Clock

I 18-bit input data port for port C.

I CLKA is a continuous clock that synchronizes all data transfers through Port A

and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA

are all synchronized to the LOW-to-HIGH transition of CLKA.

CLKB

Port B Clock

I CLKB is a continuous clock that synchronizes all data transfers through Port B

and can be asynchronous or coincident to CLKA. EFB/ORB and AEB are all synchro-

nized to the LOW-to-HIGH transition of CLKB.

CLKC

Port C Clock

I CLKC is a continuous clock that synchronizes all data transfers through Port C

and can be asynchronous or coincident to CLKA. FFC/IRC, and AFC are all synchro-

nized to the LOW-to-HIGH transition of CLKC.

CSA

CSB

EFA/ORA

Port A Chip

Select

Port B Chip

Select

Port A

Empty/Output

Ready Flag

I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write

on Port A. The A0−35 outputs are in the high-impedance state when CSA is HIGH.

I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write

on Port B. The B0–17 outputs are in the high-impedance state when CSB is HIGH.

O This is a dual-function pin. In the CY Standard Mode, the EFA function is selected.

EFA indicates whether or not the FIFO2 memory is empty. In the FWFT Mode, the ORA

function is selected. ORA indicates the presence of valid data on A0−35 outputs,

available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of

CLKA.[1]

EFB/ORB

Port B

Empty/Output

Ready Flag

O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected.

EFB indicates whether or not the FIFO1 memory is empty. In the FWFT Mode, the ORB

function is selected. ORB indicates the presence of valid data on B0–17 outputs,

available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of

CLKB.[1]

ENA

Port A Enable

I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write

data on Port A.

ENB

Port B Enable

I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write

data on Port B.

FFA/IRA

Port A Full/Input O This is a dual-function pin. In the CY Standard Mode, the FFA function is selected.

Ready Flag

FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA

function is selected. IRA indicates whether or not there is space available for writing to

the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

FFC/IRC

Port C Full/Input O This is a dual-function pin. In the CY Standard Mode, the FFC function is selected. FFC

Ready Flag

indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function

is selected. IRC indicates whether or not there is space available for writing to the

FIFO2 memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKB.

Notes:

1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary

flag (e.g., in bursts), use CY standard mode.

2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer to

“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.

Document #: 38-06023 Rev. *C

Page 4 of 39

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