CY7C43686-10AC 查看數據表（PDF） - Cypress Semiconductor
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CY7C43686-10AC Datasheet PDF : 39 Pages
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CY7C43646
CY7C43666
CY7C43686
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty flag to reflect the new level of fill. Therefore, the
Almost Empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFC)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almost full, almost or full–1. The Almost Full state is defined by
the contents of register Y1 for AFA and register Y2 for AFC.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the number of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X6 respectively. An Almost Full
flag is HIGH when the number of words in its FIFO is less than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)] for
the CY7C436X6 respectively.[2]
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B/Port C without
putting it in queue. The Mailbox Select (MBA, MBB, MBC)
inputs choose between a mail register and a FIFO for a port
data transfer operation. The usable width of both the Mail1 and
Mail2 registers matches the selected bus size for Port C.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH.
When sending data from Port C to Port A via the Mail2 register,
the following is the case: A LOW-to-HIGH transition on CLKC
writes C0-17 data to the Mail2 register when a Port C write is
selected by WENC with MBC HIGH. If the selected Port C bus
size is also 18 bits, then the usable width of the Mail2 register
employs data lines C0-17. If the selected Port C bus size is 9
bits, then the usable width of the Mail2 register employs data
lines C0-8. (In this case, C9-17 are “Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, RENB, and ENB with MBB HIGH. For an
18-bit bus size, 18 bits of mailbox data are placed on B0–17.
For a 9-bit bus size, 9 bits of mailbox data are placed on B0–8.
(In this case, B9-17 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B and Port C buses can be configured in a 18-bit word
or 9-bit byte format for data read from FIFO1 or written to
FIFO2. The levels applied to the Port B Bus Size Select
(SIZEB) and the Port C Bus Size Select (SIZEC) determine the
width of the buses. The bus size can be selected indepen-
dently for Ports B and C. These levels should be static
throughout FIFO operation. Both bus size selections are
implemented at the completion of Master Reset, by the time
the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either byte
or word-size. They are referred to as Big Endian (most signif-
icant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1 and MRS2 selects the
endian method that will be active during FIFO operation. BE is
a “don’t care” input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436X6. Bus-matching operations
are done after data is read from the FIFO1 RAM and before
data is written to FIFO2 RAM. These bus-matching operations
are not available when transferring data via mailbox registers.
Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be “don’t care” inputs. For example, when a
word-size bus is selected, then mailbox data can be trans-
mitted only between A0-17 and B0-17. When a byte-size bus is
selected, then mailbox data can be transmitted only between
A0-8 and B0-8.
Document #: 38-06023 Rev. *C
Page 9 of 39
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