MAX17528 查看數據表（PDF） - Maxim Integrated

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MAX17528

1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers

Maxim Integrated 

1-Phase Quick-PWM

Intel IMVP-6.5/GMCH Controllers

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =

GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless other-

wise specified.) (Note 2)

PARAMETER

GATE DRIVERS

DH Gate-Driver On-Resistance

DL Gate-Driver On-Resistance

SYMBOL

CONDITIONS

RON(DH)

RON(DL)

BST - LX forced

to 5V

High state (pullup)

Low state (pulldown)

High state (pullup)

Low state (pulldown)

MIN TYP MAX UNITS

2.5



2.0

2.0



0.7

Internal BST Switch

On-Resistance

RBST IBST = 10mA, VDD = 5V

20



CURRENT MONITOR

Current-Monitor

Transconductance

Gm(IMON)

IIMON/
(VCSP - VCSN),

VCSN = 0.45V to 2.0V

4.9

5.1

mS

Current-Monitor Offset

Referred to V(CSP, CSN)

IIMON = 0

-1.5

+1.5

mV

IMON Clamp Voltage

LOGIC AND I/O

Logic-Input High Voltage

Logic-Input Low Voltage

Low-Voltage Logic-

Input High Voltage

VIMON IIMON = -1mA

VIH

VIL

VIHLV

PGDIN

PGDIN

SHDN, SKIP, SLOW, D0–D6

1.05

2.3

0.67

1.15

V

V

1.0

V

V

Low-Voltage Logic-

Input Low Voltage

VILLV SHDN, SKIP, SLOW, D0–D6

0.33

V

CLKEN Logic-Input High Voltage

for IMVP-6.5 Startup

2.3

V

CLKEN Logic-Input Low Voltage

for GMCH

1.0

V

Note 2: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design

and characterization.

Note 3: The equation for the target voltage VTARGET is:

VTARGET = the slew-rate-controlled version of VDAC, where VDAC = 0V for shutdown, VDAC = VBOOT (IMVP-6.5) or VVID

(GMCH) during startup, and VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 2).

In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.

Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced

to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times can be

different due to MOSFET switching speeds.

8 _______________________________________________________________________________________

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