MAX2410E/D 查看數據表（PDF） - Maxim Integrated

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MAX2410E/D

Low-Cost RF Up/Downconverter with LNA and PA Driver

Maxim Integrated 

Low-Cost RF Up/Downconverter

with LNA and PA Driver

______________________________________________________________Pin Description

PIN

1, 3, 4, 12,

14, 18, 20,

23, 28

2

5, 10

6

7

8

9

11

13

15, 17

16

19

21

22

24

25

26

27

NAME

GND

LNAIN

VCC

RXEN

LO

LO

TXEN

GC

PADROUT

GND

PADRIN

TXMXOUT

IFOUT

IFIN

RXMXIN

GND

GND

LNAOUT

FUNCTION

Ground. Connect to PC board ground plane with minimal inductance.

RF Input to the LNA. AC couple to this pin. At 1.9GHz, LNAIN can be easily matched to 50Ω with one

external shunt 1pF capacitor.

Supply Voltage (2.7V to 5.5V). Bypass VCC to GND at each pin with a 47pF capacitor as close to each

pin as possible.

Logic-Level Enable for Receiver Circuitry. A logic high turns on the receiver. When TXEN and RXEN are

both at a logic high, the part is placed in standby mode, with a supply current of 160µA (typical). If

TXEN and RXEN are both at a logic low, the part is set to shutdown mode, with a supply current of

0.1µA (typical).

50Ω Local-Oscillator (LO) Input Port. AC couple to this pin.

50Ω Inverting Local-Oscillator Input Port. For single-ended operation connect LO directly to GND. If a

differential LO signal is available, AC couple the inverted LO signal to this pin.

Logic-Level Enable for Transmitter Circuitry. A logic high turns on the transmitter. When TXEN and

RXEN are both at a logic high, the part is placed in standby mode, with 160µA (typical) supply current.

If TXEN and RXEN are both at a logic low, the part is set to shutdown mode, with 0.1µA (typical) supply

current.

Gain-Control Input for Power-Amplifier Driver. By applying an analog control voltage between 0V and

2.15V, the gain of the PA driver can be adjusted over a 35dB range. Connect to VCC for maximum gain.

Power-Amplifier Driver Output. AC couple to this pin. Use external shunt inductor to VCC to match this pin

to 50Ω. This also provides DC bias. See the Typical Operating Characteristics for a plot of PADROUT

Impedance vs. Frequency.

Power-Amplifier Driver Input Ground. Connect to PC board ground plane with minimal inductance.

RF Input to Variable-Gain Power-Amplifier Driver. AC couple to this pin. Internally matched to 50Ω. This

input typically provides a 2:1 VSWR at 1.9GHz. See the Typical Operating Characteristics for a plot of

PADRIN Impedance vs. Frequency.

RF Output of Transmit Mixer (Upconverter). AC couple to this pin. Use an external shunt inductor to

VCC as part of a matching network to 50Ω. This also provides DC bias. See the Typical Operating

Characteristics for a plot of TXMXOUT Impedance vs. Frequency.

IF Output of Receive Mixer (Downconverter). AC couple to this pin. This output is an open collector and

should be pulled up to VCC with an inductor. This inductor can be part of the matching network to the

desired IF impedance. Alternatively, a resistor can be placed in parallel to this inductor to set a termi-

nating impedance. See the Typical Operating Circuit for more information.

IF Input of Transmit Mixer (Upconverter). AC couple to this pin. IFIN presents a high input impedance

and typically requires a matching network. See the Typical Operating Characteristics for a plot of IFIN

Impedance vs. Frequency.

RF Input to Receive Mixer (Downconverter). AC couple to this pin. This input typically requires a matching

network for connecting to an external filter. See the Typical Operating Characteristics for a plot of RXMXIN

Impedance vs. Frequency.

Receive Mixer Input Ground. Connect to PC board ground plane with minimal inductance.

LNA Output Ground. Connect to PC board ground plane with minimal inductance.

LNA Output. AC couple to this pin. This output typically provides a VSWR of better than 2:1 at frequen-

cies from 1.7GHz to 3GHz with no external matching components. At other frequencies, a matching

network may be required to match this pin to an external filter. Consult the Typical Operating

Characteristics for a plot of LNA Output Impedance vs. Frequency.

8 _______________________________________________________________________________________

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