MAX2441EAI 查看數據表（PDF） - Maxim Integrated

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MAX2441EAI

900MHz Image-Reject Receivers

Maxim Integrated 

900MHz Image-Reject Receivers

PIN

1

2

3

4, 9,

12–15

5

6

7

8

10

11

16

17

18

19

20

21

22

23

24

25

NAME

VCC

CAP1

RXOUT

GND

RXIN

VCC

GND

GND

LNAGAIN

VCC

RXON

VCOON

DIV1

MOD

PREGND

PREOUT

VCC

VCC

TANK

TANK

Pin Description

FUNCTION

Supply-Voltage Input for Master Bias Cell. Bypass with a 47pF low-inductance capacitor and 0.1µF to

GND (pin 28 recommended).

Receive Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01µF to GND.

Do not make any other connections to this pin.

Single-Ended, 330Ω IF Output. AC couple to this pin.

Ground Connection

Receiver RF Input, single-ended. The input match shown in Figure 1 maintains an input VSWR of better

than 2:1 from 902MHz to 928MHz.

Supply Voltage Input for Receive Low-Noise Amplifier. Bypass with a 47pF low-inductance capacitor to

GND (pin 7 recommended).

Ground Connection for Receive Low-Noise Amplifier. Connect directly to ground plane using multiple vias.

Ground Connection for Signal-Path Blocks, except LNA. Connect directly to ground plane.

Low-Noise Amplifier Gain-Control Input. Drive this pin high for maximum gain. When LNAGAIN is pulled

low, the LNA is capacitively bypassed and the supply current is reduced by 4.5mA. This pin can also be

driven with an analog voltage to adjust the LNA gain in intermediate states. Refer to the Receiver Gain

vs. LNAGAIN Voltage graph in the Typical Operating Characteristics, as well as Table 1.

Supply Voltage Input for Signal-Path Blocks, except LNA. Bypass with a 47pF low-inductance capacitor

and 0.01µF to GND (pin 8 recommended).

Driving RXON with a logic high enables the LNA, receive mixer, and IF output buffer. VCOON must also

be high.

Driving VCOON with a logic high turns on the VCO, phase shifters, VCO buffers, and prescaler. The

prescaler can be selectively disabled by floating the PREGND pin.

Driving DIV1 with a logic high disables the divide-by-64/65 prescaler and connects the PREOUT pin

directly to an oscillator buffer amplifier, which outputs -8dBm into a 50Ω load. Tie DIV1 low for divide-by-

64/65 operation. Pull this pin low when in shutdown to minimize off current.

Modulus Control for the Divide-by-64/65 Prescaler: high = divide-by-64, low = divide-by-65. Note that

the DIV1 pin must be at logic low when using the prescaler mode.

Ground connection for the Prescaler. Tie PREGND to ground for normal operation. Leave floating to

disable the prescaler and the output buffer. Tie MOD and DIV1 to ground and leave PREOUT floating

when disabling the prescaler.

Prescaler/Oscillator Buffer Output. In divide-by-64/65 mode (DIV1 = low), the output level is 500mVp-p

into a high-impedance load. In divide-by-1 mode (DIV1 = high), this output delivers -8dBm into a 50Ω

load. AC couple to this pin.

Supply-Voltage Input for Prescaler. Bypass with a 47pF low-inductance capacitor and 0.01µF to GND

(pin 20 recommended).

Supply-Voltage Input for VCO and Phase Shifters. Bypass with a 47pF low-inductance capacitor to GND

(pin 26 recommended).

Differential Oscillator Tank Port. See Applications Information for information on tank circuits or on using

an external oscillator.

Differential Oscillator Tank Port. See Applications Information for information on tank circuits or on using

an external oscillator.

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