0.5Ω, Low-Voltage, Single-Supply
SPST Analog Switches
Test Circuits/Timing Diagrams
MAX4626
MAX4627
MAX4628
VN_
NO
OR NC
LOGIC
INPUT
IN
GND
V+
V+
COM
VOUT
RL
CL
50Ω
35pF
LOGIC VINH
INPUT VINL
SWITCH 0V
OUTPUT
tr < 5ns
tf < 5ns
50%
tOFF
VOUT 0.9 · V0UT
0.9 · VOUT
tON
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 2. Switching Time
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4626
MAX4627
MAX4628
VGEN
RGEN NC
OR NO
GND
V+
V+
COM
IN
VINL to VINH
Figure 3. Charge Injection
+5V 10nF
0V OR V+
IN
V+
COM
MAX4626
MAX4627
MAX4628
NO
GND
VOUT
CL
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
VIN
50Ω USE
ONLY FOR
ISOLATION
VOUT
NETWORK
ANALYZER
50Ω
50Ω
MEAS
50Ω
REF
50Ω
OFF-ISOLATION
=
20log
VOUT
VIN
ON-LOSS = 20log VOUT
VIN
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND “OFF” NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND “ON” NO_ OR NC_TERMINAL ON EACH SWITCH.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 4. On-Loss and Off-Isolation
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