MB86613S 查看數據表（PDF） - Fujitsu
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MB86613S Datasheet PDF : 134 Pages
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Preliminary
3.2.21. BUS Management CSR Initialization
These registers keep initial value of bandwidth_available and channel_available_hi/lo registers.
BY hardware reset, software reset and Bus reset these registers values are loaded to band width_available
and channel_available_hi/lo registers.
31
24 23
16 15
87
0
InitialBandwidthAvailable
Bit
----
12:0
Field Name
--------------
InitialBandwidthAvailable
rscu
----
rw
reset
--------
1333h
description
-----------------------------------
These bits specify the initial value of
bandwidth_available register.
31
24 23
16 15
87
0
InitialChannelAvailableHi
Bit
----
31:0
Field Name
--------------
InitialChannelAvailableHi
rscu
----
rw
reset
description
-------- -----------------------------------
FFFFFFFFh These bits specify the initial value of
Channel_available_Hi register.
31
24 23
16 15
87
0
InitialChannelAvailableLo
Bit
----
31:0
Field Name
--------------
InitialChannelAvailableLo
rscu
----
rw
reset
description
-------- -----------------------------------
FFFFFFFFh These bits specify the initial value of
Channel_available_Lo register.
40
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