MC100EP57(2014) 查看數據表（PDF） - ON Semiconductor
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MC100EP57 Datasheet PDF : 10 Pages
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MC10EP57, MC100EP57
VCC SEL1 SEL0 VCC
Q
20
19
18
17
16
Q
VCC VBB1 VBB2 VEE
15
14
13
12
11
4:1
1
2
VCC D0
3
4
5
6
7
8
9
10
D0 D1
D1
D2
D2
D3
D3
VEE
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Package (Top View) and Logic Diagram
D0 VCC VCC SEL1 SEL0
20 19 18 17 16
Exposed Pad
D0 1
D1 2
D1 3
D2 4
D2 5
MC10/100EP57
15 VCC
14 Q
13 Q
12 VCC
11 VBB1
6
7 8 9 10
NOTE:
D3 D3 VEE VEE VBB2
The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to VEE.
Figure 1. QFN−20 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0 − 3*, D0 − 3*
ECL Differential Data Inputs
SEL0*, SEL1*
ECL MUX Select Inputs
VBB1, VBB2
Q, Q
ECL Reference Output Voltage
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed Pad
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
SEL1
SEL0
L
L
L
H
H
L
H
H
DATA OUT
D0, D0
D1, D1
D2, D2
D3, D3
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