MC145484 查看數據表（PDF） - Motorola => Freescale
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MC145484 Datasheet PDF : 26 Pages
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FST (FSR)
BCLKT (BCLKR)
DT
1 2 3 4 5 6 78
DR DON’T CARE 1 2 3 4 5 6 7 8
DON’T CARE
Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)
FST (FSR)
BCLKT (BCLKR)
DT
1 2 3 4 5 6 78
DR DON’T CARE 1 2 3 4 5 6 7 8
DON’T CARE
Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)
IDL SYNC (FST)
IDL CLOCK (BCLKT)
IDL TX (DT)
1 2 3 4 5 6 78
1 2 3 4 5 6 78
IDL RX (DR)
DON’T CARE 1
2
3
4
5
6
7
8
DON’T
CARE
1
2
3
4
5
6
7
8
DON’T
CARE
B1–CHANNEL (FSR = 0)
B2–CHANNEL (FSR = 1)
Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking)
FSC (FST)
DCL (BCLKT)
Dout (DT)
1 2 3 4 5 6 78 1 2 3 4 5 6 78
Din (DR)
DON’T
CARE
1 2 3 4 5 6 7 81 2 3 4 5 6 78
DON’T CARE
B1–CHANNEL (FSR = 0)
B2–CHANNEL (FSR = 1)
Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking)
Figure 2. Digital Timing Modes for the PCM Data Interface
MOTOROLA
MC145484
7
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