HI3306 查看數據表（PDF） - Intersil
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HI3306 Datasheet PDF : 16 Pages
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HI3306
Pin Descriptions
PIN NUMBER
PDIP
SOIC
1
1
2
2
3
3, 4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13, 14
13
15
14
16
15
17
16
18
17
19
18
20
NAME
B6
OF
VSS
VZ
CE2
CE1
CLK
Phase
VREF +
VREF -
VIN
VDD
B1
B2
B3
REF(CTR)
B4
B5
DESCRIPTION
Bit 6, Output (MSB).
Overflow, Output.
Digital Ground.
Zener Reference Output.
Three-State Output Enable Input, Active Low. See Table 1.
Three-State Output Enable Input, Active High. See Table 1.
Clock Input.
Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs
when the clock is low and “Auto Balance” occurs when the clock is high (see text).
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Signal Input.
Power Supply, +5V.
Bit 1, Output (LSB).
Bit 2, Output.
Bit 3, Output.
Reference Ladder Midpoint.
Bit 4, Output.
Bit 5, Output.
TABLE 1. CHIP ENABLE TRUTH TABLE
CE1
CE2
0
1
1
1
X
0
X = Don’t care
B1 - B6
Valid
Three-State
Three-State
OF
Valid
Valid
Three-State
TABLE 2. OUTPUT CODE TABLE
(NOTE 6)
INPUT VOLTAGE
BINARY OUTPUT CODE (LSB)
CODE DESCRIPTION
VREF VREF VREF VREF
6.40 5.12 4.80 3.20
(V)
(V)
(V)
(V) OF B6 B5 B4 B3 B2 B1
DECIMAL
COUNT
Zero
1 LSB
2 LSB
0.00 0.00 0.00 0.00 0
0
0
0
0
0
0
0
0.10 0.08 0.075 0.05 0
0
0
0
0
0
1
1
0.20 0.16 0.15 0.10 0
0
0
0
0
1
0
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1/2 Full Scale - 1 LSB
3.10 2.48 2.325 1.55 0
0
1
1
1
1
1
31
1/2 Full Scale
3.20 2.56 2.40 1.60 0
1
0
0
0
0
0
32
1/2 Full Scale + 1 LSB
3.30 2.64 2.475 1.65 0
1
0
0
0
0
1
33
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Scale - 1 LSB
6.20 4.96 4.65 3.10 0
1
1
1
1
1
0
62
Full Scale
6.30 5.04 4.725 3.15 0
1
1
1
1
1
1
63
Overflow
6.40 5.12 4.80 3.20 1
1
1
1
1
1
1
127
NOTE:
6. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
8
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