MC92501 查看數據表（PDF） - Motorola => Freescale

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MC92501

ATM Cell Processor

Motorola => Freescale 

MC92501

Table 1-4. Processor Interface Signals (Continued)

Signal

Name

Signal

Type

Detailed Description

MDTACK0–

MDTACK1

Output

MP Data Acknowledge 0–1— These tri-statable output signals are used

to indicate the end of an access from the MC92501. At the end of each

access, this signal is actively pulled up and then released. The user may

program the MC92501 not to drive this signal during certain types of

accesses. This signal is output asynchronously to MCLK.

MDATA0–

MDATA31

Input/Output MP Data Bus— This tri-state bidirectional bus provides the general data

path between the MC92501 and the microprocessor.

MINT

Output

MP Interrupt— This output signal is used to notify the microprocessor of

the occurrence of interrupting events. This signal is asserted on the

rising edge of ACLK (asynchronous with respect to MCLK).

MREQ0

Output

MP Request 0— This output signal can be programmed to one of three

options (described below in note 2). Its default value is option #1: MP

Cell In Request (MCIREQ).

MREQ1

Output

MP Request 1— This output signal can be programmed to one of three

options (described below in note 2). Its default value is option #2: MP

Cell Out Request (MCOREQ)..

MREQ2

Output

MP Request 2— This output signal can be programmed to one of of

three options (described below in note 2). Its default value is option #3:

External Memory Maintenance Request (EMMREQ).

Notes: 1.

2.

All inputs are 5 V tolerant.

MREQ0, MREQ1 and MREQ2 signals are fully backward compatible to the MC92501

Revision A MCIREQ, MCOREQ and EMMREQ signals, respectively. The MREQ[n]

signals are used by DMA devices and can be programmed to support DMA requests as

follows:

— MP Cell In Request: MREQ[n] is an output signal that can be used by an external DMA

device as a control line indicating when to start a new cell insertion cycle into the

MC92501. It is asserted whenever the Cell Insertion Register array is available to be

written. This signal is output on the falling edge of MCLK.

— MP Cell Out Request: MREQ[n] is an output signal may be used by an external DMA

device as a control line indicating when to start a new cell extraction cycle from the

MC92501. It is asserted whenever the Cell Extraction Register array is available to be

read. It is output on the falling edge of MCLK.

— External Memory Maintenance Request: MREQ[n] is an output signal is asserted a

programmable number of clock cycles before the start of an External Memory

maintenance cycle. It is deasserted after a programmable number of maintenance

accesses have been performed. It is output on the falling edge of MCLK.

MOTOROLA

MC92501 Data Sheet

1-5

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