MCM67D709FN16 查看數據表（PDF） - Motorola => Freescale
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MCM67D709FN16 Datasheet PDF : 12 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE (See Note 1)
Processor Frequency
60 MHz
50 MHz
MCM67D709–16 MCM67D709–20
Parameter
Symbol
Min
Max
Min
Max Unit Notes
Read Cycle Time Clock High to Clock High
tKHKH
16
—
20
—
ns 1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
ns
Clock High to Output Valid
tKHQV
—
6
—
7.5
ns
3
Clock (K) High to Output Low Z After Write
tKHQX1
0
—
0
—
ns
Output Hold from Clock High
tKHQX2
2
—
3
—
ns 3, 4
Setup Times:
A
tAVKL
2
—
2
—
ns
W tWHKH
2
2
PIE tPIEHKH
2
2
SIE tSIEHKH
2
2
Hold Times:
A
tKLAX
2
—
2
—
ns
W tKHWX
2
2
PIE tKHPIEX
2
2
SIE tKHSIEX
2
2
Output Enable High to Q High–Z
tPOEHQZ
0
6
0
8
ns
4
tSOEHQZ
Output Hold from Output Enable High
tPOEHQX
2
—
5
—
ns
4
tSOEHQX
Output Enable Low to Q Active
tPOELQX
0
—
0
—
ns
4
tSOELQX
Output Enable Low to Output Valid
tPOELQV
—
5
—
6
ns
tSOELQV
NOTES:
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K, SOE, or POE.
3. K must be at a high level for outputs to transition.
4. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for
a given device.
OUTPUT
AC SPEC LOADS
RL = 50 Ω
Z0 = 50 Ω
VL = 1.5 V
Figure 1A
OUTPUT
255 Ω
+5V
480 Ω
5 pF
Figure 1B
MCM67D709
4
MOTOROLA FAST SRAM
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