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MCP3903

Six Channel Delta Sigma A/D Converter

Microchip Technology 

MCP3903

1.0 ELECTRICAL

CHARACTERISTICS

The Reliability Targets section includes the absolute

maximum ratings for the device, defining the values

that will cause no long term damage regardless of

duration.

These tables also represent the testing requirements

per the Max. and Min. columns.

1.1 RELIABILITY TARGETS

ABSOLUTE MAXIMUM RATINGS †

VDD ................................................................................... 7.0V

Digital inputs and outputs w.r.t. AGND ........-0.6V to VDD +0.6V

Analog input w.r.t. AGND..................................... ....-6V to +6V

VREF input w.r.t. AGND................................-0.6V to VDD +0.6V

Storage temperature ..................................... -65°C to +150°C

Ambient temp. with power applied................ -65°C to +125°C

Soldering temperature of leads (10 seconds)............. +300°C

ESD on the analog inputs (HBM,MM)................. 5.0 kV, 500V

ESD on all other pins (HBM,MM)........................ 5.0 kV, 500V

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to

3.6V, Internal VREF, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C,

GAIN = 1, VIN = 1VPP = 353mVRMS @ 50/60 Hz.

Param.

Num.

Symbol

Characteristic

Min. Typ. Max. Units

Test Conditions

Internal Voltage Reference

A001

A002

A003

VREF

TCREF

ZOUTREF

Voltage

Tempco

Output Impedance

-2% 2.35

—5

7

+2%

—

—

V VREFEXT = 0

ppm/°C VREFEXT = 0

kΩ AVDD=5V,

VREFEXT = 0

Voltage Reference Input

A004

Input Capacitance

——

10

pF

A005

A006

VREF

Differential Input Voltage

Range (VREF+ - VREF-)

2.2 —

2.6

VREF+ Absolute Voltage on REFIN+ 1.9 —

2.9

pin

V VREF = (VREF+ - VREF-),

VREFEXT = 1

V VREFEXT = 1

A007

VREF- Absolute Voltage on REFIN- -0.3 —

pin

+0.3

V VREF- should be connected

to AGND when VREFEXT=0

ADC Performance

A008

Resolution (No Missing

Codes)

24

bits OSR = 256 (see Table 5-2)

A009

fS

Sampling Frequency

See Table 4-2

kHz fS = DMCLK = MCLK / (4 x

PRESCALE)

A010

fD

Output Data Rate

See Table 4-2

ksps

fD = DRCLK= DMCLK / OSR

= MCLK / (4 x PRESCALE x

OSR)

Note 1:

2:

3:

4:

5:

6:

7:

8:

This specification implies that the ADC output is valid over this entire differential range, i.e. there is no distortion or

instability across this input range. Dynamic Performance is specified at -0.5 dB below the maximum signal range,

VIN = -0.5 dBFS @ 50/60 Hz = 333 mVRMS, VREF = 2.4V.

See terminology section for definition.

This parameter is established by characterization and not 100% tested.

For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 000000, RESET<5:0> = 000000; VREFEXT = 0, CLKEXT = 0.

For these operating currents, the following configuration bit settings apply: Config Register Settings:

SHUTDOWN<5:0> = 111111, VREFEXT = 1, CLKEXT = 1.

Applies to all gains. Offset error is dependant on PGA gain setting.

Outside of this range, ADC accuracy is not specified. An extended input range of +/- 6V can be applied continuously to

the part with no risk for damage.

For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with BOOST bits

off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a

crystal, CLKEXT bit should be equal to ‘0’.

© 2011 Microchip Technology Inc.

DS25048B-page 3

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